> -Original Message-
> From: Ville Syrjälä
> Sent: Thursday, December 2, 2021 6:37 PM
> To: Srinivas, Vidya
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width
>
> On Thu, Dec 02, 2021 at 04:38:36PM +0530, Vidya Srinivas
On Thu, Dec 02, 2021 at 04:38:36PM +0530, Vidya Srinivas wrote:
> PLANE_CUS_CTL has a restriction of 4096 width even though
> PLANE_SIZE and scaler size registers supports max 5120.
> Take care of this restriction in max_width.
>
> Without this patch, when 5k content is sent on HDR plane
> with
> -Original Message-
> From: Ville Syrjälä
> Sent: Thursday, December 2, 2021 4:43 PM
> To: Srinivas, Vidya
> Cc: intel-gfx@lists.freedesktop.org; Yashashvi, Shantam
>
> Subject: Re: [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width
>
> On Thu, Dec 02, 2021 at 11:10:37AM
PLANE_CUS_CTL has a restriction of 4096 width even though
PLANE_SIZE and scaler size registers supports max 5120.
Take care of this restriction in max_width.
Without this patch, when 5k content is sent on HDR plane
with NV12 content, FIFO underrun is seen and screen blanks
out.
v2: Addressed
On Thu, Dec 02, 2021 at 11:10:37AM +, Srinivas, Vidya wrote:
>
>
> > -Original Message-
> > From: Ville Syrjälä
> > Sent: Thursday, December 2, 2021 4:26 PM
> > To: Srinivas, Vidya
> > Cc: intel-gfx@lists.freedesktop.org; Yashashvi, Shantam
> >
> > Subject: Re: [PATCH] drm/i915:
> -Original Message-
> From: Ville Syrjälä
> Sent: Thursday, December 2, 2021 4:26 PM
> To: Srinivas, Vidya
> Cc: intel-gfx@lists.freedesktop.org; Yashashvi, Shantam
>
> Subject: Re: [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width
>
> On Thu, Dec 02, 2021 at 03:25:34AM
On Thu, Dec 02, 2021 at 03:25:34AM +, Srinivas, Vidya wrote:
>
>
> > -Original Message-
> > From: Ville Syrjälä
> > Sent: Wednesday, December 1, 2021 8:33 PM
> > To: Srinivas, Vidya
> > Cc: intel-gfx@lists.freedesktop.org; Yashashvi, Shantam
> >
> > Subject: Re: [PATCH] drm/i915:
> -Original Message-
> From: Ville Syrjälä
> Sent: Wednesday, December 1, 2021 8:33 PM
> To: Srinivas, Vidya
> Cc: intel-gfx@lists.freedesktop.org; Yashashvi, Shantam
>
> Subject: Re: [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width
>
> On Wed, Dec 01, 2021 at 09:17:27AM
On Wed, Dec 01, 2021 at 09:17:27AM +0530, Vidya Srinivas wrote:
> PLANE_CUS_CTL has a restriction of 4096 width even though
> PLANE_SIZE and scaler size registers supports max 5120.
> Take care of this restriction in max_width.
>
> Without this patch, when 5k content is sent on HDR plane
> with
PLANE_CUS_CTL has a restriction of 4096 width even though
PLANE_SIZE and scaler size registers supports max 5120.
Take care of this restriction in max_width.
Without this patch, when 5k content is sent on HDR plane
with NV12 content, FIFO underrun is seen and screen blanks
out.
v2: Addressed
PLANE_CUS_CTL has a restriction of 4096 width even though
PLANE_SIZE and scaler size registers supports max 5120.
Take care of this restriction in max_width.
Without this patch, when 5k content is sent on HDR plane
with NV12 content, FIFO underrun is seen and screen blanks
out.
v2: Addressed
> -Original Message-
> From: Ville Syrjälä
> Sent: Tuesday, November 30, 2021 11:40 PM
> To: Srinivas, Vidya
> Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma
> ; Yashashvi, Shantam
>
> Subject: Re: [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width
>
> On Tue, Nov 30,
PLANE_CUS_CTL has a restriction of 4096 width even though
PLANE_SIZE and scaler size registers supports max 5120.
Take care of this restriction in max_width.
Without this patch, when 5k content is sent on HDR plane
with NV12 content, FIFO underrun is seen and screen blanks
out.
v2: Addressed
On Tue, Nov 30, 2021 at 10:42:20PM +0530, Vidya Srinivas wrote:
> PLANE_CUS_CTL has a restriction of 4096 width even though
> PLANE_SIZE and scaler size registers supports max 5120.
> Take care of this restriction in max_width.
>
> Without this patch, when 5k content is sent on HDR plane
> with
> -Original Message-
> From: Ville Syrjälä
> Sent: Tuesday, November 30, 2021 10:00 PM
> To: Srinivas, Vidya
> Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma
> ; Yashashvi, Shantam
>
> Subject: Re: [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width
>
> On Tue, Nov 30,
PLANE_CUS_CTL has a restriction of 4096 width even though
PLANE_SIZE and scaler size registers supports max 5120.
Take care of this restriction in max_width.
Without this patch, when 5k content is sent on HDR plane
with NV12 content, FIFO underrun is seen and screen blanks
out.
v2: Addressed
PLANE_CUS_CTL has a restriction of 4096 width even though
PLANE_SIZE and scaler size registers supports max 5120.
Take care of this restriction in max_width.
Without this patch, when 5k content is sent on HDR plane
with NV12 content, FIFO underrun is seen and screen blanks
out.
v2: Addressed
On Tue, Nov 30, 2021 at 09:35:34PM +0530, Vidya Srinivas wrote:
> PLANE_CUS_CTL has a restriction of 4096 width even though
> PLANE_SIZE and scaler size registers supports max 5120.
> Take care of this restriction in max_width.
>
> Without this patch, when 5k content is sent on HDR plane
> with
PLANE_CUS_CTL has a restriction of 4096 width even though
PLANE_SIZE and scaler size registers supports max 5120.
Take care of this restriction in max_width.
Without this patch, when 5k content is sent on HDR plane
with NV12 content, FIFO underrun is seen and screen blanks
out.
Signed-off-by:
19 matches
Mail list logo
