On Tue, Jun 23, 2015 at 02:14:26PM -0700, Bob Paauwe wrote:
The registers and process differ from other platforms. If the hardware
was programmed incorrectly, this will return invalid cdclk values, which
should then cause reprogramming of the hardware.
v2(Matt): Return 19.2 MHz when DE PLL
On Wed, Jun 24, 2015 at 03:49:22PM +0300, Ville Syrjälä wrote:
On Tue, Jun 23, 2015 at 02:14:26PM -0700, Bob Paauwe wrote:
The registers and process differ from other platforms. If the hardware
was programmed incorrectly, this will return invalid cdclk values, which
should then cause
The registers and process differ from other platforms. If the hardware
was programmed incorrectly, this will return invalid cdclk values, which
should then cause reprogramming of the hardware.
v2(Matt): Return 19.2 MHz when DE PLL is disabled (Ville)
v3: Make less assumptions about the hardware
