On Thu, Sep 25, 2014 at 04:34:42PM +, Runyan, Arthur J wrote:
That was a fast fix. Looks good now.
Reviewed-by: Arthur Runyan arthur.j.run...@intel.com
Both merged, thanks for patchesreview.
-Daniel
v2: Arthur noticed I was changing the wrong bit.
Cc: Arthur Runyan
BDW display - DP buffer translation values changed to give better margin.
Further change to entry 6; set dword 0 bit 31=1.
Both changes were approved already but this one didn't landed BSpec yet
this is why it is in a separated patch. Making reviewer's life easier.
Also alowing separated tests
That was a fast fix. Looks good now.
Reviewed-by: Arthur Runyan arthur.j.run...@intel.com
v2: Arthur noticed I was changing the wrong bit.
Cc: Arthur Runyan arthur.j.run...@intel.com
Cc: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
