>-Original Message-
>From: Vivi, Rodrigo
>Sent: Friday, April 10, 2015 11:40 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo; R, Durgadoss; Runyan, Arthur J
>Subject: [PATCH] drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logic
>
>Since the beginning there is a missunderstanding on t
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6179
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -2
Intel-gfx] [PATCH] drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT
logic
Hi Durga, are you ok with this one?
Hi Art, do you believe there is any risk of avoiding TP when panel
tells DP_PSR_NO_TRAIN_ON_EXIT and link is disabled? I believe on the
other discussion we conluded that DP_PSR_NO_TRAIN_ON_EXI
Hi Durga, are you ok with this one?
Hi Art, do you believe there is any risk of avoiding TP when panel
tells DP_PSR_NO_TRAIN_ON_EXIT and link is disabled? I believe on the
other discussion we conluded that DP_PSR_NO_TRAIN_ON_EXIT was only
responsible for TP configurations regardless links standby
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5962
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 275/275
Since the begining there is a missunderstanding on the meaning of this
dpcd bit.
This bit shouldn't indicate whether to use link standby or not, but just
be used to configure TP1, TP2 and TP3 times and tell hw aux should be skiped
since HW is the responsible one.
Even with help of frontbuffer trac
