Re: [Intel-gfx] [PATCH] drm/i915: Refresh cached DP port register value on resume

2016-06-22 Thread Ville Syrjälä
On Fri, Jun 17, 2016 at 09:40:45PM +0300, Imre Deak wrote: > On Fri, 2016-05-13 at 20:53 +0300, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > During hibernation the cached DP port register value will be left with > > whatever value we have

Re: [Intel-gfx] [PATCH] drm/i915: Refresh cached DP port register value on resume

2016-06-17 Thread Imre Deak
On Fri, 2016-05-13 at 20:53 +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > During hibernation the cached DP port register value will be left with > whatever value we have there when we create the hibernation image. > Currently that means the

[Intel-gfx] [PATCH] drm/i915: Refresh cached DP port register value on resume

2016-05-13 Thread ville . syrjala
From: Ville Syrjälä During hibernation the cached DP port register value will be left with whatever value we have there when we create the hibernation image. Currently that means the port (and eDP PLL) will be off in the cached value. However when we resume there