Re: [Intel-gfx] [PATCH] drm/i915: Revert workaround for disabling L3 cache aging on BYT

2014-02-20 Thread Jesse Barnes
On Wed, 19 Feb 2014 13:09:31 -0800 Sinclair Yeh sinclair@intel.com wrote: V2: edit the commit message to contain more info The W/A spreadsheet says this is still required, but the b-spec says it's not for BYT-T. So the documentation is not clear. However, our experience with the other

[Intel-gfx] [PATCH] drm/i915: Revert workaround for disabling L3 cache aging on BYT

2014-02-19 Thread Sinclair Yeh
V2: edit the commit message to contain more info The W/A spreadsheet says this is still required, but the b-spec says it's not for BYT-T. So the documentation is not clear. However, our experience with the other SKUs of BYT-I/M on Android and Linux suggests that setting this bit actually causes