On Mon, Jan 11, 2016 at 01:09:50PM +0530, Goel, Akash wrote:
>
>
> On 1/10/2016 11:09 PM, Chris Wilson wrote:
> >On Sat, Jan 09, 2016 at 05:00:21PM +0530, akash.g...@intel.com wrote:
> >>From: Akash Goel
> >>
> >>Gen9 has an additional address translation hardware support
On 1/11/2016 2:19 PM, Chris Wilson wrote:
On Mon, Jan 11, 2016 at 01:09:50PM +0530, Goel, Akash wrote:
On 1/10/2016 11:09 PM, Chris Wilson wrote:
On Sat, Jan 09, 2016 at 05:00:21PM +0530, akash.g...@intel.com wrote:
From: Akash Goel
Gen9 has an additional address
On 1/10/2016 11:09 PM, Chris Wilson wrote:
On Sat, Jan 09, 2016 at 05:00:21PM +0530, akash.g...@intel.com wrote:
From: Akash Goel
Gen9 has an additional address translation hardware support in form of
Tiled Resource Translation Table (TR-TT) which provides an extra
On Sat, Jan 09, 2016 at 05:00:21PM +0530, akash.g...@intel.com wrote:
> From: Akash Goel
>
> Gen9 has an additional address translation hardware support in form of
> Tiled Resource Translation Table (TR-TT) which provides an extra level
> of abstraction over PPGTT.
> This
From: Akash Goel
Gen9 has an additional address translation hardware support in form of
Tiled Resource Translation Table (TR-TT) which provides an extra level
of abstraction over PPGTT.
This is useful for mapping Sparse/Tiled texture resources.
Sparse resources are created