[Intel-gfx] [PATCH] intel: Fix stencil buffer to be W tiled

2011-07-18 Thread Chad Versace
Until now, the stencil buffer was allocated as a Y tiled buffer, because in several locations the PRM states that it is. However, it is actually W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Format: W-Major Tile Format is used for separate stencil. The GTT

Re: [Intel-gfx] [PATCH] intel: Fix stencil buffer to be W tiled

2011-07-18 Thread Eric Anholt
On Mon, 18 Jul 2011 00:55:03 -0700, Chad Versace wrote: > diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c > b/src/mesa/drivers/dri/intel/intel_fbo.c > index 1669af2..507cc33 100644 > --- a/src/mesa/drivers/dri/intel/intel_fbo.c > +++ b/src/mesa/drivers/dri/intel/intel_fbo.c > @@ -173,6 +173,9

Re: [Intel-gfx] [PATCH] intel: Fix stencil buffer to be W tiled

2011-07-18 Thread Paul Menzel
Am Montag, den 18.07.2011, 00:55 -0700 schrieb Chad Versace: […] > diff --git a/src/mesa/drivers/dri/intel/intel_span.c > b/src/mesa/drivers/dri/intel/intel_span.c > index 153803f..d306432 100644 > --- a/src/mesa/drivers/dri/intel/intel_span.c > +++ b/src/mesa/drivers/dri/intel/intel_span.c > @@

[Intel-gfx] [PATCH] intel: Fix stencil buffer to be W tiled

2011-07-18 Thread Chad Versace
Until now, the stencil buffer was allocated as a Y tiled buffer, because in several locations the PRM states that it is. However, it is actually W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Format: W-Major Tile Format is used for separate stencil. The GTT

[Intel-gfx] [PATCH] intel: Fix stencil buffer to be W tiled

2011-07-18 Thread Chad Versace
Chad Versace (2): xf86-video-intel dri: Do not tile stencil buffer src/intel_dri.c | 16 mesa intel: Fix stencil buffer to be W tiled src/mesa/drivers/dri/intel/intel_clear.c |6 ++ src/mesa/drivers/dri/intel/intel_context.c |9 ++-