Vandita,
As we discussed earlier, we need to select clock for PORT_B as well
in dual link video scenario even though we are going to use same DPLL for both
the
Ports. This will be done by DPCLKA_CFGCR0_DDI_CLK_SEL.
icl_map_plls_to_ports inside haswell_crtc_enable() doesn't take care of that
as
ICL DSI uses DPLL.
As per the discussion with hw team, the same
sequence can be used for enabling DPLL for mipi dsi
as well. Hence reusing the dpll functions from icl pll manager.
In addition to that we need to program
the esc clock register before enabling dsi.
This has been tested on
