On Thu, Mar 05, 2015 at 09:19:48PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Poke at the CBR1_VLV register during init_clock_gating to make sure the
> PND deadline scheme is used.
>
> The hardware has two modes of operation wrt. watermarks:
>
> 1) PND deadline mode:
From: Ville Syrjälä
Poke at the CBR1_VLV register during init_clock_gating to make sure the
PND deadline scheme is used.
The hardware has two modes of operation wrt. watermarks:
1) PND deadline mode:
- memory request deadline is calculated from actual FIFO level * DDL
- WM1 watermark values a
On Fri, Feb 27, 2015 at 12:38:44PM -0800, Jesse Barnes wrote:
> On 02/10/2015 05:28 AM, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Poke at the CBR1_VLV register during init_clock_gating to make sure the
> > PND deadline scheme is used.
> >
> > The hardware has two modes
On 02/10/2015 05:28 AM, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Poke at the CBR1_VLV register during init_clock_gating to make sure the
> PND deadline scheme is used.
>
> The hardware has two modes of operation wrt. watermarks:
>
> 1) PND deadline mode:
> - memory reques
From: Ville Syrjälä
Poke at the CBR1_VLV register during init_clock_gating to make sure the
PND deadline scheme is used.
The hardware has two modes of operation wrt. watermarks:
1) PND deadline mode:
- memory request deadline is calculated from actual FIFO level * DDL
- WM1 watermark values a
