Re: [Intel-gfx] [PATCH 1/2] drm/i915/icl: Implement gen11 flush including tile cache

2019-08-13 Thread Chris Wilson
Quoting Mika Kuoppala (2019-08-13 08:57:51) > Chris Wilson writes: > > > Quoting Mika Kuoppala (2019-08-12 17:01:07) > >> @@ -2829,7 +2887,10 @@ int intel_execlists_submission_setup(struct > >> intel_engine_cs *engine) > >> logical_ring_default_irqs(engine); > >> > >> if

Re: [Intel-gfx] [PATCH 1/2] drm/i915/icl: Implement gen11 flush including tile cache

2019-08-13 Thread Mika Kuoppala
Chris Wilson writes: > Quoting Mika Kuoppala (2019-08-12 17:01:07) >> Add tile cache flushing for gen11. To relive us from the >> burden of previous obsolete workarounds, make a dedicated >> flush/invalidate callback for gen11. >> >> To fortify an independent single flush, do post >> sync op as

Re: [Intel-gfx] [PATCH 1/2] drm/i915/icl: Implement gen11 flush including tile cache

2019-08-12 Thread Chris Wilson
Quoting Mika Kuoppala (2019-08-12 17:01:07) > Add tile cache flushing for gen11. To relive us from the > burden of previous obsolete workarounds, make a dedicated > flush/invalidate callback for gen11. > > To fortify an independent single flush, do post > sync op as there are indications that

[Intel-gfx] [PATCH 1/2] drm/i915/icl: Implement gen11 flush including tile cache

2019-08-12 Thread Mika Kuoppala
Add tile cache flushing for gen11. To relive us from the burden of previous obsolete workarounds, make a dedicated flush/invalidate callback for gen11. To fortify an independent single flush, do post sync op as there are indications that without it we don't flush everything. This should also make