On Mon, Nov 02, 2020 at 08:59:32AM -0800, Aditya Swarup wrote:
On 10/26/20 9:35 PM, Lucas De Marchi wrote:
On Mon, Oct 26, 2020 at 09:32:26PM -0700, Lucas De Marchi wrote:
DG1 uses 2 registers for the ddi clock mapping, with PHY A and B using
DPCLKA_CFGCR0 and PHY C and D using DPCLKA1_CFGCR0.
On 10/26/20 9:35 PM, Lucas De Marchi wrote:
> On Mon, Oct 26, 2020 at 09:32:26PM -0700, Lucas De Marchi wrote:
>> DG1 uses 2 registers for the ddi clock mapping, with PHY A and B using
>> DPCLKA_CFGCR0 and PHY C and D using DPCLKA1_CFGCR0. Hide this behind a
>> single macro that chooses the
On Mon, Oct 26, 2020 at 09:32:26PM -0700, Lucas De Marchi wrote:
DG1 uses 2 registers for the ddi clock mapping, with PHY A and B using
DPCLKA_CFGCR0 and PHY C and D using DPCLKA1_CFGCR0. Hide this behind a
single macro that chooses the correct register according to the phy
being accessed, use
DG1 uses 2 registers for the ddi clock mapping, with PHY A and B using
DPCLKA_CFGCR0 and PHY C and D using DPCLKA1_CFGCR0. Hide this behind a
single macro that chooses the correct register according to the phy
being accessed, use the correct bitfields for each pll/phy and implement
separate
