On Wed, 03 Oct 2018, Manasi Navare wrote:
> This patch set only updates them in case of few registers.
> All the other MASKS and SHIFTS clean up for all i915 registers
> as a follow up right?
Let's see if we can agree this is the direction we want to go first.
BR,
Jani.
--
Jani Nikula, Intel
This seems really useful for the DSC PPS bitfields in i915_reg.h
since its a lot of bitfileds mapped from the spec to the macros for
for MASKS and SHIFTS for 128 bytes of PPS data.
This patch set only updates them in case of few registers.
All the other MASKS and SHIFTS clean up for all i915
On Wed, Oct 03, 2018 at 07:05:21PM +0300, Jani Nikula wrote:
> Introduce REG_BIT(n) to define register bits and REG_FIELD_MASK(h, l) to
> define register field masks.
>
> We define the above as wrappers to BIT() and GENMASK() respectively to
> force u32 type to go with our register size.
Introduce REG_BIT(n) to define register bits and REG_FIELD_MASK(h, l) to
define register field masks.
We define the above as wrappers to BIT() and GENMASK() respectively to
force u32 type to go with our register size. Additionally, the specified
type will be helpful with follow-up to define and
