Re: [Intel-gfx] [PATCH 1/4] drm/i915: read dpcd 0 - 12 & link_status always

2015-09-04 Thread Daniel Vetter
On Thu, Sep 03, 2015 at 03:25:04PM +0300, Jani Nikula wrote: > On Wed, 02 Sep 2015, Daniel Vetter wrote: > > On Tue, Sep 01, 2015 at 01:16:49PM +0300, Jani Nikula wrote: > >> On Thu, 27 Aug 2015, Sivakumar Thulasimani > >> wrote: > >> > From:

Re: [Intel-gfx] [PATCH 1/4] drm/i915: read dpcd 0 - 12 & link_status always

2015-09-03 Thread Jani Nikula
On Wed, 02 Sep 2015, Daniel Vetter wrote: > On Tue, Sep 01, 2015 at 01:16:49PM +0300, Jani Nikula wrote: >> On Thu, 27 Aug 2015, Sivakumar Thulasimani >> wrote: >> > From: "Thulasimani,Sivakumar" >> > >> >

Re: [Intel-gfx] [PATCH 1/4] drm/i915: read dpcd 0 - 12 & link_status always

2015-09-02 Thread Daniel Vetter
On Tue, Sep 01, 2015 at 01:16:49PM +0300, Jani Nikula wrote: > On Thu, 27 Aug 2015, Sivakumar Thulasimani > wrote: > > From: "Thulasimani,Sivakumar" > > > > Compliance requires the driver to read dpcd register 0 to 12 and > >

Re: [Intel-gfx] [PATCH 1/4] drm/i915: read dpcd 0 - 12 & link_status always

2015-09-01 Thread Jani Nikula
On Thu, 27 Aug 2015, Sivakumar Thulasimani wrote: > From: "Thulasimani,Sivakumar" > > Compliance requires the driver to read dpcd register 0 to 12 and > registers 0x200 to 0x205 to be read always. > Current code performs dpcd

[Intel-gfx] [PATCH 1/4] drm/i915: read dpcd 0 - 12 link_status always

2015-08-27 Thread Sivakumar Thulasimani
From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com Compliance requires the driver to read dpcd register 0 to 12 and registers 0x200 to 0x205 to be read always. Current code performs dpcd read for short pulse interrupts only if the sink is enabled. This patch forces read for link status