> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: 01 September 2023 18:35
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 11/12] drm/i915: Assert that VRR is off during
> vblank evasion if necessary
>
> From: Ville Syrjälä
>
> Whenever we
Reviewed-by: Manasi Navare
Manasi
On Fri, Sep 1, 2023 at 6:05 AM Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> Whenever we change the actual transcoder timings (clock via
> seamless M/N, full modeset, (or soon) vtotal via LRR) we
> want the timing generator to be in non-VRR during the
From: Ville Syrjälä
Whenever we change the actual transcoder timings (clock via
seamless M/N, full modeset, (or soon) vtotal via LRR) we
want the timing generator to be in non-VRR during the commit.
Warn if we forgot to turn VRR off prior to vblank evasion.
Cc: Manasi Navare
Signed-off-by:
