[Intel-gfx] [PATCH 11/25] drm/i915/guc: Implement parallel context pin / unpin functions

2021-10-14 Thread Matthew Brost
Parallel contexts are perma-pinned by the upper layers which makes the backend implementation rather simple. The parent pins the guc_id and children increment the parent's pin count on pin to ensure all the contexts are unpinned before we disable scheduling with the GuC / or deregister the

Re: [Intel-gfx] [PATCH 11/25] drm/i915/guc: Implement parallel context pin / unpin functions

2021-10-14 Thread John Harrison
On 10/13/2021 13:42, Matthew Brost wrote: Parallel contexts are perma-pinned by the upper layers which makes the backend implementation rather simple. The parent pins the guc_id and children increment the parent's pin count on pin to ensure all the contexts are unpinned before we disable

[Intel-gfx] [PATCH 11/25] drm/i915/guc: Implement parallel context pin / unpin functions

2021-10-13 Thread Matthew Brost
Parallel contexts are perma-pinned by the upper layers which makes the backend implementation rather simple. The parent pins the guc_id and children increment the parent's pin count on pin to ensure all the contexts are unpinned before we disable scheduling with the GuC / or deregister the