Re: [Intel-gfx] [PATCH 12/15] drm/i915: Zero out HOWM registers before writing new WM/HOWM register values

2016-12-02 Thread Ville Syrjälä
On Thu, Dec 01, 2016 at 03:43:07PM +0100, Maarten Lankhorst wrote: > Op 28-11-16 om 18:37 schreef ville.syrj...@linux.intel.com: > > From: Ville Syrjälä > > > > On VLV/CHV some of the watermark values are split across two registers: > > low order bits in one, and

Re: [Intel-gfx] [PATCH 12/15] drm/i915: Zero out HOWM registers before writing new WM/HOWM register values

2016-12-01 Thread Maarten Lankhorst
Op 28-11-16 om 18:37 schreef ville.syrj...@linux.intel.com: > From: Ville Syrjälä > > On VLV/CHV some of the watermark values are split across two registers: > low order bits in one, and high order bits in another. So we may not be > able to update a single

[Intel-gfx] [PATCH 12/15] drm/i915: Zero out HOWM registers before writing new WM/HOWM register values

2016-11-28 Thread ville . syrjala
From: Ville Syrjälä On VLV/CHV some of the watermark values are split across two registers: low order bits in one, and high order bits in another. So we may not be able to update a single watermark value atomically, and thus we must be careful that we don't