Re: [Intel-gfx] [PATCH 12/16] drm/i915/guc/slpc: Cache platform frequency limits for slpc

2021-07-20 Thread Belgaumkar, Vinay
On 7/10/2021 11:15 AM, Michal Wajdeczko wrote: On 10.07.2021 03:20, Vinay Belgaumkar wrote: Cache rp0, rp1 and rpn platform limits into slpc structure for range checking while setting min/max frequencies. Also add "soft" limits which keep track of frequency changes made from userland.

Re: [Intel-gfx] [PATCH 12/16] drm/i915/guc/slpc: Cache platform frequency limits for slpc

2021-07-17 Thread Belgaumkar, Vinay
On 7/10/2021 11:15 AM, Michal Wajdeczko wrote: On 10.07.2021 03:20, Vinay Belgaumkar wrote: Cache rp0, rp1 and rpn platform limits into slpc structure for range checking while setting min/max frequencies. Also add "soft" limits which keep track of frequency changes made from userland.

Re: [Intel-gfx] [PATCH 12/16] drm/i915/guc/slpc: Cache platform frequency limits for slpc

2021-07-10 Thread Michal Wajdeczko
On 10.07.2021 03:20, Vinay Belgaumkar wrote: > Cache rp0, rp1 and rpn platform limits into slpc structure > for range checking while setting min/max frequencies. > > Also add "soft" limits which keep track of frequency changes > made from userland. These are initially set to platform min > and

[Intel-gfx] [PATCH 12/16] drm/i915/guc/slpc: Cache platform frequency limits for slpc

2021-07-09 Thread Vinay Belgaumkar
Cache rp0, rp1 and rpn platform limits into slpc structure for range checking while setting min/max frequencies. Also add "soft" limits which keep track of frequency changes made from userland. These are initially set to platform min and max. Signed-off-by: Vinay Belgaumkar ---