[Intel-gfx] [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

2018-02-21 Thread Vidya Srinivas
If the fb format is YUV, enable the plane CSC mode bits for the conversion. v2: Addressed review comments from Shashank Sharma Alignment issue fixed in i915_reg.h v3: Adding Reviewed By from Shashank Sharma Reviewed-by: Shashank Sharma Signed-off-by: Vidya Srinivas

Re: [Intel-gfx] [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

2018-02-15 Thread Sharma, Shashank
My previous review comment for alignment is not addressed in this patch. Regards Shashank On 2/14/2018 10:27 AM, Vidya Srinivas wrote: If the fb format is YUV, enable the plane CSC mode bits for the conversion. Signed-off-by: Vidya Srinivas ---

Re: [Intel-gfx] [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

2018-02-15 Thread Sharma, Shashank
My previous review comment for alignment has not been addressed in this series Regards Shashank On 2/14/2018 10:27 AM, Vidya Srinivas wrote: If the fb format is YUV, enable the plane CSC mode bits for the conversion. Signed-off-by: Vidya Srinivas ---

[Intel-gfx] [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

2018-02-14 Thread Vidya Srinivas
If the fb format is YUV, enable the plane CSC mode bits for the conversion. Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_reg.h | 6 ++ drivers/gpu/drm/i915/intel_display.c | 2 ++ 2 files changed, 8 insertions(+) diff --git

[Intel-gfx] [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

2018-02-13 Thread Vidya Srinivas
If the fb format is YUV, enable the plane CSC mode bits for the conversion. Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_reg.h | 6 ++ drivers/gpu/drm/i915/intel_display.c | 2 ++ 2 files changed, 8 insertions(+) diff --git

[Intel-gfx] [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

2018-02-13 Thread Vidya Srinivas
If the fb format is YUV, enable the plane CSC mode bits for the conversion. Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_reg.h | 6 ++ drivers/gpu/drm/i915/intel_display.c | 2 ++ 2 files changed, 8 insertions(+) diff --git

Re: [Intel-gfx] [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

2018-02-08 Thread Sharma, Shashank
Regards Shashank On 2/6/2018 6:28 PM, Vidya Srinivas wrote: If the fb format is YUV, enable the plane CSC mode bits for the conversion. Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_reg.h | 6 ++ drivers/gpu/drm/i915/intel_display.c | 2 ++

[Intel-gfx] [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

2018-02-06 Thread Vidya Srinivas
If the fb format is YUV, enable the plane CSC mode bits for the conversion. Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_reg.h | 6 ++ drivers/gpu/drm/i915/intel_display.c | 2 ++ 2 files changed, 8 insertions(+) diff --git

[Intel-gfx] [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

2018-02-06 Thread Vidya Srinivas
If the fb format is YUV, enable the plane CSC mode bits for the conversion. Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_reg.h | 6 ++ drivers/gpu/drm/i915/intel_display.c | 2 ++ 2 files changed, 8 insertions(+) diff --git

[Intel-gfx] [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

2018-01-22 Thread Vidya Srinivas
If the fb format is YUV, enable the plane CSC mode bits for the conversion. Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_reg.h | 6 ++ drivers/gpu/drm/i915/intel_display.c | 2 ++ 2 files changed, 8 insertions(+) diff --git