On Fri, Oct 19, 2018 at 05:52:14PM -0700, Souza, Jose wrote:
> On Thu, 2018-10-18 at 15:16 -0700, Manasi Navare wrote:
> > In case of Legacy DP connector on TypeC port, the
> > flex IO DPMLE register is set to number of lanes configured
> > by the display driver which will be programmed into
On Thu, 2018-10-18 at 15:16 -0700, Manasi Navare wrote:
> In case of Legacy DP connector on TypeC port, the
> flex IO DPMLE register is set to number of lanes configured
> by the display driver which will be programmed into DDI_BUF_CTL
> PORT_WIDTH_SELECTION.
> This needs to be programmed before
In case of Legacy DP connector on TypeC port, the
flex IO DPMLE register is set to number of lanes configured
by the display driver which will be programmed into DDI_BUF_CTL
PORT_WIDTH_SELECTION.
This needs to be programmed before enabling the shared PLLs hence
add a pre_pll_enable hook for ICL