Re: [Intel-gfx] [PATCH 2/2] drm/i915/ICL: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hook

2018-10-22 Thread Manasi Navare
On Fri, Oct 19, 2018 at 05:52:14PM -0700, Souza, Jose wrote: > On Thu, 2018-10-18 at 15:16 -0700, Manasi Navare wrote: > > In case of Legacy DP connector on TypeC port, the > > flex IO DPMLE register is set to number of lanes configured > > by the display driver which will be programmed into

Re: [Intel-gfx] [PATCH 2/2] drm/i915/ICL: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hook

2018-10-19 Thread Souza, Jose
On Thu, 2018-10-18 at 15:16 -0700, Manasi Navare wrote: > In case of Legacy DP connector on TypeC port, the > flex IO DPMLE register is set to number of lanes configured > by the display driver which will be programmed into DDI_BUF_CTL > PORT_WIDTH_SELECTION. > This needs to be programmed before

[Intel-gfx] [PATCH 2/2] drm/i915/ICL: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hook

2018-10-18 Thread Manasi Navare
In case of Legacy DP connector on TypeC port, the flex IO DPMLE register is set to number of lanes configured by the display driver which will be programmed into DDI_BUF_CTL PORT_WIDTH_SELECTION. This needs to be programmed before enabling the shared PLLs hence add a pre_pll_enable hook for ICL