Re: [Intel-gfx] [PATCH 2/2] drm/i915: Don't rely that 2 VDSC engines are always enough for pixel rate

On Mon, Jul 10, 2023 at 11:37:56AM +0530, Nautiyal, Ankit K wrote: > > On 7/4/2023 6:47 PM, Stanislav Lisovskiy wrote: > > We are currently having FIFO underruns happening for kms_dsc test case, > > problem is that, we check if curreny cdclk is >= pixel rate only if > > there is a single VDSC

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Don't rely that 2 VDSC engines are always enough for pixel rate

On 7/4/2023 6:47 PM, Stanislav Lisovskiy wrote: We are currently having FIFO underruns happening for kms_dsc test case, problem is that, we check if curreny cdclk is >= pixel rate only if there is a single VDSC engine enabled(i.e dsc_split=false) however if we happen to have 2 VDSC engines

[Intel-gfx] [PATCH 2/2] drm/i915: Don't rely that 2 VDSC engines are always enough for pixel rate

We are currently having FIFO underruns happening for kms_dsc test case, problem is that, we check if curreny cdclk is >= pixel rate only if there is a single VDSC engine enabled(i.e dsc_split=false) however if we happen to have 2 VDSC engines enabled, we just kinda rely that this would be

[Intel-gfx] [PATCH 2/2] drm/i915: Don't rely that 2 VDSC engines are always enough for pixel rate

We are currently having FIFO underruns happening for kms_dsc test case, problem is that, we check if curreny cdclk is >= pixel rate only if there is a single VDSC engine enabled(i.e dsc_split=false) however if we happen to have 2 VDSC engines enabled, we just kinda rely that this would be