Re: [Intel-gfx] [PATCH 3/4] drm/i915: expose EU topology through sysfs

2017-11-17 Thread Lionel Landwerlin
On 17/11/17 10:53, Chris Wilson wrote: Quoting Lionel Landwerlin (2017-11-16 16:00:03) With the introduction of asymetric slices in CNL, we cannot rely on the previous SUBSLICE_MASK getparam. Here we introduce a more detailed way of querying the Gen's GPU topology that doesn't aggregate

Re: [Intel-gfx] [PATCH 3/4] drm/i915: expose EU topology through sysfs

2017-11-17 Thread Lionel Landwerlin
On 17/11/17 11:17, Chris Wilson wrote: Quoting Lionel Landwerlin (2017-11-17 11:08:07) On 17/11/17 10:53, Chris Wilson wrote: Is this subslicing only for the render unit; are all platforms going to have the same fusing across all units? At the least, I thought we would be able to configure the

Re: [Intel-gfx] [PATCH 3/4] drm/i915: expose EU topology through sysfs

2017-11-17 Thread Chris Wilson
Quoting Lionel Landwerlin (2017-11-17 11:08:07) > On 17/11/17 10:53, Chris Wilson wrote: > > Is this subslicing only for the render unit; are all platforms going to > > have the same fusing across all units? At the least, I thought we would > > be able to configure the powergating of the different

Re: [Intel-gfx] [PATCH 3/4] drm/i915: expose EU topology through sysfs

2017-11-17 Thread Lionel Landwerlin
On 17/11/17 10:53, Chris Wilson wrote: Quoting Lionel Landwerlin (2017-11-16 16:00:03) With the introduction of asymetric slices in CNL, we cannot rely on the previous SUBSLICE_MASK getparam. Here we introduce a more detailed way of querying the Gen's GPU topology that doesn't aggregate

Re: [Intel-gfx] [PATCH 3/4] drm/i915: expose EU topology through sysfs

2017-11-17 Thread Chris Wilson
Quoting Lionel Landwerlin (2017-11-16 16:00:03) > With the introduction of asymetric slices in CNL, we cannot rely on > the previous SUBSLICE_MASK getparam. Here we introduce a more detailed > way of querying the Gen's GPU topology that doesn't aggregate numbers. > > This is essential for

Re: [Intel-gfx] [PATCH 3/4] drm/i915: expose EU topology through sysfs

2017-11-17 Thread Lionel Landwerlin
On 17/11/17 09:37, Tvrtko Ursulin wrote: On 16/11/2017 16:00, Lionel Landwerlin wrote: With the introduction of asymetric slices in CNL, we cannot rely on the previous SUBSLICE_MASK getparam. Here we introduce a more detailed way of querying the Gen's GPU topology that doesn't aggregate

Re: [Intel-gfx] [PATCH 3/4] drm/i915: expose EU topology through sysfs

2017-11-17 Thread Tvrtko Ursulin
On 16/11/2017 16:00, Lionel Landwerlin wrote: With the introduction of asymetric slices in CNL, we cannot rely on the previous SUBSLICE_MASK getparam. Here we introduce a more detailed way of querying the Gen's GPU topology that doesn't aggregate numbers. This is essential for monitoring parts

[Intel-gfx] [PATCH 3/4] drm/i915: expose EU topology through sysfs

2017-11-16 Thread Lionel Landwerlin
With the introduction of asymetric slices in CNL, we cannot rely on the previous SUBSLICE_MASK getparam. Here we introduce a more detailed way of querying the Gen's GPU topology that doesn't aggregate numbers. This is essential for monitoring parts of the GPU with the OA unit, because signals