Re: [Intel-gfx] [PATCH 33/67] drm/i915: Configure DPLL's for Cannonlake

2017-05-04 Thread Ander Conselvan De Oliveira
On Thu, 2017-04-06 at 12:15 -0700, Rodrigo Vivi wrote: > From: "Kahola, Mika" > > DPLL's are defined in DPCLKA_CFGCR0 register (0x6C200). Let's use these > definitions when computing dpll's for ddi ports. > > v2: (Rodrigo) Remove register that was defined in another patch

[Intel-gfx] [PATCH 33/67] drm/i915: Configure DPLL's for Cannonlake

2017-04-06 Thread Rodrigo Vivi
From: "Kahola, Mika" DPLL's are defined in DPCLKA_CFGCR0 register (0x6C200). Let's use these definitions when computing dpll's for ddi ports. v2: (Rodrigo) Remove register that was defined in another patch with fixed name and more bits. Signed-off-by: Kahola, Mika