Re: [Intel-gfx] [PATCH 4/7] drm/i915/bdw: cs-stall before state cache invld w/a

2014-08-05 Thread Ville Syrjälä
On Mon, Aug 04, 2014 at 11:15:16AM -0700, Rodrigo Vivi wrote: > From: Ben Widawsky > > We do this already for previous GENs. I guess we must do it for BDW too > according to DOCS. > > "Pipe_control with CS-stall bit set must be issued before a > pipe-control command that has the State Cache Inva

[Intel-gfx] [PATCH 4/7] drm/i915/bdw: cs-stall before state cache invld w/a

2014-08-04 Thread Rodrigo Vivi
From: Ben Widawsky We do this already for previous GENs. I guess we must do it for BDW too according to DOCS. "Pipe_control with CS-stall bit set must be issued before a pipe-control command that has the State Cache Invalidate bit set." This does not solve the problem I have unfortunately. I d