Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/perf: fix ctx_id read with GuC & ICL

2018-06-01 Thread Michel Thierry
On 6/1/2018 10:08 AM, Lionel Landwerlin wrote: On 01/06/18 16:18, Chris Wilson wrote: Quoting Lionel Landwerlin (2018-06-01 10:52:15) + /* +* The LRCA is aligned to a page. As a result the +* lower 12bits are always at 0 and

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/perf: fix ctx_id read with GuC & ICL

2018-06-01 Thread Lionel Landwerlin
On 01/06/18 16:18, Chris Wilson wrote: Quoting Lionel Landwerlin (2018-06-01 10:52:15) + /* +* The LRCA is aligned to a page. As a result the +* lower 12bits are always at 0 and reused in the +*

[Intel-gfx] [PATCH v2 2/2] drm/i915/perf: fix ctx_id read with GuC & ICL

2018-06-01 Thread Lionel Landwerlin
One thing we didn't really understand about the OA report is that the ContextID field (dword 2) is copy of the context descriptor (dword 1). On Gen8->10 and without using GuC we didn't notice the issue because we only checked the 21bits of the ContextID field in the OA reports which matches