Re: [Intel-gfx] [PATCH v2 4/5] drm/i915: master irq pvmmio optimization

2018-10-31 Thread Zhang, Xiaolin
Ping review. Thanks very much. BRs, Xiaolin -Original Message- From: Zhang, Xiaolin Sent: Friday, October 19, 2018 3:27 PM To: intel-gfx@lists.freedesktop.org Cc: intel-gvt-...@lists.freedesktop.org; Zhang, Xiaolin ; Zhenyu Wang ; Wang, Zhi A ; Chris Wilson ; Joonas Lahtinen ; He;

[Intel-gfx] [PATCH v2 4/5] drm/i915: master irq pvmmio optimization

2018-10-19 Thread Xiaolin Zhang
Master irq register is accessed twice every irq handling, then trapped to SOS very frequently. Optimize it by moving master irq register to share page, writing don't need be trapped. When need enable irq to let SOS inject irq timely, use another pvmmio register to achieve this purpose. So avoid