On Tue, Dec 11, 2018 at 04:18:47PM +0200, Ville Syrjälä wrote:
> On Tue, Dec 11, 2018 at 11:40:43AM +0200, Imre Deak wrote:
> > On Wed, Dec 05, 2018 at 06:32:22PM +0200, Imre Deak wrote:
> > > On Tue, Dec 04, 2018 at 03:41:09PM -0800, clinton.a.tay...@intel.com
> > > wrote:
> > > > From: Clint
On Tue, Dec 11, 2018 at 11:40:43AM +0200, Imre Deak wrote:
> On Wed, Dec 05, 2018 at 06:32:22PM +0200, Imre Deak wrote:
> > On Tue, Dec 04, 2018 at 03:41:09PM -0800, clinton.a.tay...@intel.com wrote:
> > > From: Clint Taylor
> > >
> > > In August 2018 the BSPEC changed the ICL port programming
On Wed, Dec 05, 2018 at 06:32:22PM +0200, Imre Deak wrote:
> On Tue, Dec 04, 2018 at 03:41:09PM -0800, clinton.a.tay...@intel.com wrote:
> > From: Clint Taylor
> >
> > In August 2018 the BSPEC changed the ICL port programming sequence to
> > closely resemble earlier gen programming sequence.
> >
On Tue, Dec 04, 2018 at 03:41:09PM -0800, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor
>
> In August 2018 the BSPEC changed the ICL port programming sequence to
> closely resemble earlier gen programming sequence.
>
> v2: remove debug code that Imre found
> v3: simplify translation
From: Clint Taylor
In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence.
v2: remove debug code that Imre found
v3: simplify translation table if-else
BSpec: 21257
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Rodrigo Vivi
