On Thu, Sep 25, 2014 at 10:03:53AM -0700, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor
>
> Haswell and later silicon has added a new pixel replication register
> to the pipe timings for each transcoder. Now in addition to the
> DPLL_A_MD register for the pixel clock double, we also need
>> > So did you verify that the register really is a transcoder register?
>> > Eg. set PIPE_MULT(A) to >1x and use pipe A to drive the EDP transcoder.
>>
>> I did not verify. This change was done based on the fact that the
>> register does not exist in the VPG HTML version of the BPEC for
>> Trans
On Fri, Sep 26, 2014 at 03:04:22PM -0700, Clint Taylor wrote:
> On 09/26/2014 09:38 AM, Ville Syrjälä wrote:
> > On Thu, Sep 25, 2014 at 10:03:53AM -0700, clinton.a.tay...@intel.com wrote:
> >> From: Clint Taylor
> >>
> >> Haswell and later silicon has added a new pixel replication register
> >> t
On 09/26/2014 09:38 AM, Ville Syrjälä wrote:
On Thu, Sep 25, 2014 at 10:03:53AM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Haswell and later silicon has added a new pixel replication register
to the pipe timings for each transcoder. Now in addition to the
DPLL_A_MD register fo
On Thu, Sep 25, 2014 at 10:03:53AM -0700, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor
>
> Haswell and later silicon has added a new pixel replication register
> to the pipe timings for each transcoder. Now in addition to the
> DPLL_A_MD register for the pixel clock double, we also need
From: Clint Taylor
Haswell and later silicon has added a new pixel replication register
to the pipe timings for each transcoder. Now in addition to the
DPLL_A_MD register for the pixel clock double, we also need to write
to the TRANS_MULT_n (0x6002c) register to double the pixel data. Writing
to
