On Mon, 11 Apr 2016, Chris Wilson wrote:
On Mon, Apr 11, 2016 at 04:02:17PM +0100, Peter Antoine wrote:
+ for (index = 0, offset = 0; index < size; index++, offset += 4)
+ {
+ batch[offset] = MI_STORE_REGISTER_MEM_64_BIT_ADDR;
+ batch[offset+1] =
On Mon, Apr 11, 2016 at 04:02:17PM +0100, Peter Antoine wrote:
> >>+ for (index = 0, offset = 0; index < size; index++, offset += 4)
> >>+ {
> >>+ batch[offset] = MI_STORE_REGISTER_MEM_64_BIT_ADDR;
> >>+ batch[offset+1] = reg_base + (index * sizeof(uint32_t));
> >>+
On Mon, 11 Apr 2016, Chris Wilson wrote:
On Mon, Apr 11, 2016 at 01:51:25PM +0100, Peter Antoine wrote:
The MOCS registers were added in Gen9 and define the caching policy.
The registers are split into two sets. The first set controls the
EDRAM policy and have a set for each engine, the second
On Mon, Apr 11, 2016 at 01:51:25PM +0100, Peter Antoine wrote:
> The MOCS registers were added in Gen9 and define the caching policy.
> The registers are split into two sets. The first set controls the
> EDRAM policy and have a set for each engine, the second set controls
> the L3 policy. The two
The MOCS registers were added in Gen9 and define the caching policy.
The registers are split into two sets. The first set controls the
EDRAM policy and have a set for each engine, the second set controls
the L3 policy. The two sets use the same index.
The RCS registers and the L3CC registers are
