Re: [Intel-gfx] [PATCH v3 2/4] drm/i915/psr: Account for sink CRC raciness on some panels

2017-07-14 Thread Jim Bride
On Fri, Jul 14, 2017 at 12:46:08PM +0300, Jani Nikula wrote: > On Tue, 11 Jul 2017, Jim Bride wrote: > > According to the eDP spec, when the count field in TEST_SINK_MISC > > increments then the six bytes of sink CRC information in the DPCD > > should be valid.

Re: [Intel-gfx] [PATCH v3 2/4] drm/i915/psr: Account for sink CRC raciness on some panels

2017-07-14 Thread Jani Nikula
On Tue, 11 Jul 2017, Jim Bride wrote: > According to the eDP spec, when the count field in TEST_SINK_MISC > increments then the six bytes of sink CRC information in the DPCD > should be valid. Unfortunately, this doesn't seem to be the case > on some panels, and as a

Re: [Intel-gfx] [PATCH v3 2/4] drm/i915/psr: Account for sink CRC raciness on some panels

2017-07-12 Thread Dhinakaran Pandiyan
On Tuesday, July 11, 2017 3:19:54 PM PDT Jim Bride wrote: > According to the eDP spec, when the count field in TEST_SINK_MISC > increments then the six bytes of sink CRC information in the DPCD > should be valid. Unfortunately, this doesn't seem to be the case > on some panels, and as a result we

Re: [Intel-gfx] [PATCH v3 2/4] drm/i915/psr: Account for sink CRC raciness on some panels

2017-07-11 Thread Vivi, Rodrigo
If you had sent these 2 in a separated series I believe it would had passed CI so I could merge today. Also it would be better if you want to speed up things with a bit of sense of progress since the other 2 patches in this series will probably require some rework. On Tue, 2017-07-11 at 15:19

[Intel-gfx] [PATCH v3 2/4] drm/i915/psr: Account for sink CRC raciness on some panels

2017-07-11 Thread Jim Bride
According to the eDP spec, when the count field in TEST_SINK_MISC increments then the six bytes of sink CRC information in the DPCD should be valid. Unfortunately, this doesn't seem to be the case on some panels, and as a result we get some incorrect and inconsistent values from the sink CRC DPCD