Re: [Intel-gfx] [PATCH v3 3/3] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

2018-05-24 Thread Mika Kuoppala
Oscar Mateo Lozano writes: > On 5/18/2018 3:41 PM, Yunwei Zhang wrote: >> L3Bank could be fused off in hardware for debug purpose, and it >> is possible that subslice is enabled while its corresponding L3Bank pairs >> are disabled. In such case, if MCR packet control

Re: [Intel-gfx] [PATCH v3 3/3] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

2018-05-18 Thread Oscar Mateo Lozano
On 5/18/2018 3:41 PM, Yunwei Zhang wrote: L3Bank could be fused off in hardware for debug purpose, and it is possible that subslice is enabled while its corresponding L3Bank pairs are disabled. In such case, if MCR packet control register(0xFDC) is programed to point to a disabled bank pair, a

[Intel-gfx] [PATCH v3 3/3] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

2018-05-18 Thread Yunwei Zhang
L3Bank could be fused off in hardware for debug purpose, and it is possible that subslice is enabled while its corresponding L3Bank pairs are disabled. In such case, if MCR packet control register(0xFDC) is programed to point to a disabled bank pair, a MMIO read into L3Bank range will return 0