Hi, Tiago.
On 08/26/2015 02:02 AM, Tiago Vignatti wrote:
From: Daniel Vetter daniel.vet...@ffwll.ch
The userspace might need some sort of cache coherency management e.g. when CPU
and GPU domains are being accessed through dma-buf at the same time. To
circumvent this problem there are
On Wed, Aug 26, 2015 at 08:49:00AM +0200, Thomas Hellstrom wrote:
Hi, Tiago.
On 08/26/2015 02:02 AM, Tiago Vignatti wrote:
From: Daniel Vetter daniel.vet...@ffwll.ch
The userspace might need some sort of cache coherency management e.g. when
CPU
and GPU domains are being accessed
On 08/26/2015 02:10 PM, Daniel Vetter wrote:
On Wed, Aug 26, 2015 at 08:49:00AM +0200, Thomas Hellstrom wrote:
Hi, Tiago.
On 08/26/2015 02:02 AM, Tiago Vignatti wrote:
From: Daniel Vetter daniel.vet...@ffwll.ch
The userspace might need some sort of cache coherency management e.g. when
CPU
On Wed, Aug 26, 2015 at 02:28:30PM +0200, Thomas Hellstrom wrote:
On 08/26/2015 02:10 PM, Daniel Vetter wrote:
On Wed, Aug 26, 2015 at 08:49:00AM +0200, Thomas Hellstrom wrote:
Hi, Tiago.
On 08/26/2015 02:02 AM, Tiago Vignatti wrote:
From: Daniel Vetter daniel.vet...@ffwll.ch
The
On 08/26/2015 09:58 AM, Daniel Vetter wrote:
The other is that right now there's no user nor implementation in sight
which actually does range-based flush optimizations, so I'm pretty much
expecting we'll get it wrong. Maybe instead we should go one step further
and remove the range from the
On Wed, Aug 26, 2015 at 11:32:30AM -0300, Tiago Vignatti wrote:
On 08/26/2015 09:58 AM, Daniel Vetter wrote:
The other is that right now there's no user nor implementation in sight
which actually does range-based flush optimizations, so I'm pretty much
expecting we'll get it wrong. Maybe
On 08/26/2015 04:32 PM, Tiago Vignatti wrote:
On 08/26/2015 09:58 AM, Daniel Vetter wrote:
The other is that right now there's no user nor implementation in sight
which actually does range-based flush optimizations, so I'm pretty much
expecting we'll get it wrong. Maybe instead we should go
On 08/26/2015 11:51 AM, Daniel Vetter wrote:
On Wed, Aug 26, 2015 at 11:32:30AM -0300, Tiago Vignatti wrote:
On 08/26/2015 09:58 AM, Daniel Vetter wrote:
The other is that right now there's no user nor implementation in sight
which actually does range-based flush optimizations, so I'm pretty
26 aug 2015 kl. 16:58 skrev Tiago Vignatti tiago.vigna...@intel.com:
On 08/26/2015 11:51 AM, Daniel Vetter wrote:
On Wed, Aug 26, 2015 at 11:32:30AM -0300, Tiago Vignatti wrote:
On 08/26/2015 09:58 AM, Daniel Vetter wrote:
The other is that right now there's no user nor implementation
From: Daniel Vetter daniel.vet...@ffwll.ch
The userspace might need some sort of cache coherency management e.g. when CPU
and GPU domains are being accessed through dma-buf at the same time. To
circumvent this problem there are begin/end coherency markers, that forward
directly to existing
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