Re: [Intel-gfx] [PATCH v4] drm/i915: Apply Display WA #1183 on skl, kbl, and cfl

2017-12-22 Thread Rodrigo Vivi
On Fri, Dec 22, 2017 at 09:06:28PM +, De Marchi, Lucas wrote: > On Fri, 2017-12-22 at 21:58 +0200, Ville Syrjälä wrote: > > On Mon, Dec 04, 2017 at 03:22:10PM -0800, Lucas De Marchi wrote: > > > Display WA #1183 was recently added to workaround > > > "Failures when enabling DPLL0 with eDP link

Re: [Intel-gfx] [PATCH v4] drm/i915: Apply Display WA #1183 on skl, kbl, and cfl

2017-12-22 Thread De Marchi, Lucas
On Fri, 2017-12-22 at 21:58 +0200, Ville Syrjälä wrote: > On Mon, Dec 04, 2017 at 03:22:10PM -0800, Lucas De Marchi wrote: > > Display WA #1183 was recently added to workaround > > "Failures when enabling DPLL0 with eDP link rate 2.16 > > or 4.32 GHz and CD clock frequency 308.57 or 617.14 MHz > >

Re: [Intel-gfx] [PATCH v4] drm/i915: Apply Display WA #1183 on skl, kbl, and cfl

2017-12-22 Thread Ville Syrjälä
On Mon, Dec 04, 2017 at 03:22:10PM -0800, Lucas De Marchi wrote: > Display WA #1183 was recently added to workaround > "Failures when enabling DPLL0 with eDP link rate 2.16 > or 4.32 GHz and CD clock frequency 308.57 or 617.14 MHz > (CDCLK_CTL CD Frequency Select 10b or 11b) used in this > enablin

[Intel-gfx] [PATCH v4] drm/i915: Apply Display WA #1183 on skl, kbl, and cfl

2017-12-04 Thread Lucas De Marchi
Display WA #1183 was recently added to workaround "Failures when enabling DPLL0 with eDP link rate 2.16 or 4.32 GHz and CD clock frequency 308.57 or 617.14 MHz (CDCLK_CTL CD Frequency Select 10b or 11b) used in this enabling or in previous enabling." This workaround was designed to minimize the i