On 14/09/2023 17:49, Matt Roper wrote:
On Thu, Sep 14, 2023 at 07:17:24PM +0530, Dnyaneshwar Bhadane wrote:
Set the instruction and state cache invalidate bit using INDIRECT_CTX on
every gpu context switch.
The goal of this workaround is to actually perform an explicit
invalidation of that
On Thu, Sep 14, 2023 at 07:17:24PM +0530, Dnyaneshwar Bhadane wrote:
> Set the instruction and state cache invalidate bit using INDIRECT_CTX on
> every gpu context switch.
> The goal of this workaround is to actually perform an explicit
> invalidation of that cache (by re-writing the register)
> Subject: [Intel-gfx] [PATCH v5] drm/i915: Added Wa_18022495364
>
Commit message style should be imperative so the header becomes something
Around the lines of
"Add Wa_18022495364"
> Set the instruction and state cache invalidate bit using INDIRECT_CTX on every
&
Set the instruction and state cache invalidate bit using INDIRECT_CTX on
every gpu context switch.
The goal of this workaround is to actually perform an explicit
invalidation of that cache (by re-writing the register) during every GPU
context switch, which is accomplished via a "workaround
