Re: [Intel-gfx] [PATCH v5 2/3] drm/i915: use pat_index instead of cache_level

> On Sun, May 07, 2023 at 11:39:18PM -0700, Yang, Fei wrote: >>> On Wed, May 03, 2023 at 03:50:59PM -0700, fei.y...@intel.com wrote: From: Fei Yang Currently the KMD is using enum i915_cache_level to set caching policy for buffer objects. This is flaky because the PAT index

Re: [Intel-gfx] [PATCH v5 2/3] drm/i915: use pat_index instead of cache_level

On Sun, May 07, 2023 at 11:39:18PM -0700, Yang, Fei wrote: >> On Wed, May 03, 2023 at 03:50:59PM -0700, fei.y...@intel.com wrote: >>> From: Fei Yang >>> >>> Currently the KMD is using enum i915_cache_level to set caching policy >for >>> buffer objects. This is flaky

Re: [Intel-gfx] [PATCH v5 2/3] drm/i915: use pat_index instead of cache_level

On Wed, May 03, 2023 at 03:50:59PM -0700, fei.y...@intel.com wrote: > From: Fei Yang > > Currently the KMD is using enum i915_cache_level to set caching policy for > buffer objects. This is flaky because the PAT index which really controls > the caching behavior in PTE has far more levels than

[Intel-gfx] [PATCH v5 2/3] drm/i915: use pat_index instead of cache_level

From: Fei Yang Currently the KMD is using enum i915_cache_level to set caching policy for buffer objects. This is flaky because the PAT index which really controls the caching behavior in PTE has far more levels than what's defined in the enum. In addition, the PAT index is platform dependent,