Re: [Intel-gfx] [PATCH v5 24/28] drm/i915/dp: Configure Display stream splitter registers during DSC enable

2018-10-19 Thread Manasi Navare
On Thu, Oct 18, 2018 at 08:02:14PM +0300, Ville Syrjälä wrote: > On Fri, Oct 05, 2018 at 04:23:02PM -0700, Manasi Navare wrote: > > Display Stream Splitter registers need to be programmed to enable > > the joiner if two DSC engines are used and also to enable > > the left and the right DSC

Re: [Intel-gfx] [PATCH v5 24/28] drm/i915/dp: Configure Display stream splitter registers during DSC enable

2018-10-18 Thread Ville Syrjälä
On Fri, Oct 05, 2018 at 04:23:02PM -0700, Manasi Navare wrote: > Display Stream Splitter registers need to be programmed to enable > the joiner if two DSC engines are used and also to enable > the left and the right DSC engines. This happens as part of > the DSC enabling routine in the source in

[Intel-gfx] [PATCH v5 24/28] drm/i915/dp: Configure Display stream splitter registers during DSC enable

2018-10-05 Thread Manasi Navare
Display Stream Splitter registers need to be programmed to enable the joiner if two DSC engines are used and also to enable the left and the right DSC engines. This happens as part of the DSC enabling routine in the source in atomic commit. v2: * Rebase (Manasi) Cc: Jani Nikula Cc: Ville