Re: [Intel-gfx] [PATCH v5 7/7] drm/i915: Expose RPCS (SSEU) configuration to userspace

2018-05-22 Thread Lionel Landwerlin
On 22/05/18 17:11, Lionel Landwerlin wrote: On 21/05/18 17:00, Tvrtko Ursulin wrote: + +    /* Queue this switch after all other activity */ +    list_for_each_entry(timeline, &dev_priv->gt.timelines, link) { This can iterate over gt.active_rings for a shorter walk. See current state of engi

Re: [Intel-gfx] [PATCH v5 7/7] drm/i915: Expose RPCS (SSEU) configuration to userspace

2018-05-22 Thread Lionel Landwerlin
On 21/05/18 17:00, Tvrtko Ursulin wrote: + +    /* Queue this switch after all other activity */ +    list_for_each_entry(timeline, &dev_priv->gt.timelines, link) { This can iterate over gt.active_rings for a shorter walk. See current state of engine_has_idle_kernel_context. For some reason

Re: [Intel-gfx] [PATCH v5 7/7] drm/i915: Expose RPCS (SSEU) configuration to userspace

2018-05-21 Thread Lionel Landwerlin
On 21/05/18 17:00, Tvrtko Ursulin wrote: On 21/05/2018 14:22, Lionel Landwerlin wrote: On 15/05/18 10:05, Tvrtko Ursulin wrote: On 14/05/2018 16:56, Lionel Landwerlin wrote: From: Chris Wilson We want to allow userspace to reconfigure the subslice configuration for its own use case. To d

Re: [Intel-gfx] [PATCH v5 7/7] drm/i915: Expose RPCS (SSEU) configuration to userspace

2018-05-21 Thread Tvrtko Ursulin
On 21/05/2018 14:22, Lionel Landwerlin wrote: On 15/05/18 10:05, Tvrtko Ursulin wrote: On 14/05/2018 16:56, Lionel Landwerlin wrote: From: Chris Wilson We want to allow userspace to reconfigure the subslice configuration for its own use case. To do so, we expose a context parameter to allow

Re: [Intel-gfx] [PATCH v5 7/7] drm/i915: Expose RPCS (SSEU) configuration to userspace

2018-05-21 Thread Lionel Landwerlin
On 15/05/18 10:05, Tvrtko Ursulin wrote: On 14/05/2018 16:56, Lionel Landwerlin wrote: From: Chris Wilson We want to allow userspace to reconfigure the subslice configuration for its own use case. To do so, we expose a context parameter to allow adjustment of the RPCS register stored within t

Re: [Intel-gfx] [PATCH v5 7/7] drm/i915: Expose RPCS (SSEU) configuration to userspace

2018-05-16 Thread Chris Wilson
Quoting Tvrtko Ursulin (2018-05-16 16:40:55) > > On 15/05/2018 10:05, Tvrtko Ursulin wrote: > > > > On 14/05/2018 16:56, Lionel Landwerlin wrote: > >> From: Chris Wilson > >> > >> We want to allow userspace to reconfigure the subslice configuration for > >> its own use case. To do so, we expose

Re: [Intel-gfx] [PATCH v5 7/7] drm/i915: Expose RPCS (SSEU) configuration to userspace

2018-05-16 Thread Lionel Landwerlin
On 16/05/18 16:40, Tvrtko Ursulin wrote: On 15/05/2018 10:05, Tvrtko Ursulin wrote: On 14/05/2018 16:56, Lionel Landwerlin wrote: From: Chris Wilson We want to allow userspace to reconfigure the subslice configuration for its own use case. To do so, we expose a context parameter to allow

Re: [Intel-gfx] [PATCH v5 7/7] drm/i915: Expose RPCS (SSEU) configuration to userspace

2018-05-16 Thread Tvrtko Ursulin
On 15/05/2018 10:05, Tvrtko Ursulin wrote: On 14/05/2018 16:56, Lionel Landwerlin wrote: From: Chris Wilson We want to allow userspace to reconfigure the subslice configuration for its own use case. To do so, we expose a context parameter to allow adjustment of the RPCS register stored withi

Re: [Intel-gfx] [PATCH v5 7/7] drm/i915: Expose RPCS (SSEU) configuration to userspace

2018-05-15 Thread Tvrtko Ursulin
On 14/05/2018 16:56, Lionel Landwerlin wrote: From: Chris Wilson We want to allow userspace to reconfigure the subslice configuration for its own use case. To do so, we expose a context parameter to allow adjustment of the RPCS register stored within the context image (and currently not access

[Intel-gfx] [PATCH v5 7/7] drm/i915: Expose RPCS (SSEU) configuration to userspace

2018-05-14 Thread Lionel Landwerlin
From: Chris Wilson We want to allow userspace to reconfigure the subslice configuration for its own use case. To do so, we expose a context parameter to allow adjustment of the RPCS register stored within the context image (and currently not accessible via LRI). If the context is adjusted before