Re: [Intel-gfx] [PATCH v6 1/6] drm/i915: Fallback to lower link rate and lane count during link training

2016-09-16 Thread Mika Kahola
On Thu, 2016-09-15 at 17:03 -0700, Manasi Navare wrote: > According to the DisplayPort Spec, in case of Clock Recovery failure > the link training sequence should fall back to the lower link rate > followed by lower lane count until CR succeeds. > On CR success, the sequence proceeds with Channel E

[Intel-gfx] [PATCH v6 1/6] drm/i915: Fallback to lower link rate and lane count during link training

2016-09-15 Thread Manasi Navare
According to the DisplayPort Spec, in case of Clock Recovery failure the link training sequence should fall back to the lower link rate followed by lower lane count until CR succeeds. On CR success, the sequence proceeds with Channel EQ. In case of Channel EQ failures, it should fallback to lower l