On Fri, Jul 25, 2014 at 01:28:48PM +1000, Dave Airlie wrote:
On 23 July 2014 15:11, Daniel Vetter dan...@ffwll.ch wrote:
On Sat, Jul 12, 2014 at 10:02:27AM +0530, sagar.a.kam...@intel.com wrote:
From: Borun Fu borun...@intel.com
On VLV, after i915_pm_suspend display power wells are
On 23 July 2014 15:11, Daniel Vetter dan...@ffwll.ch wrote:
On Sat, Jul 12, 2014 at 10:02:27AM +0530, sagar.a.kam...@intel.com wrote:
From: Borun Fu borun...@intel.com
On VLV, after i915_pm_suspend display power wells are staying
power ungated. So, after initiating mem sleep echo mem
On Sat, Jul 12, 2014 at 10:02:27AM +0530, sagar.a.kam...@intel.com wrote:
From: Borun Fu borun...@intel.com
On VLV, after i915_pm_suspend display power wells are staying
power ungated. So, after initiating mem sleep echo mem /sys/power/state
Display is staing D0 State. There might be better
On Sat, Jul 12, 2014 at 10:02:27AM +0530, sagar.a.kam...@intel.com wrote:
From: Borun Fu borun...@intel.com
On VLV, after i915_pm_suspend display power wells are staying
power ungated. So, after initiating mem sleep echo mem /sys/power/state
Display is staing D0 State. There might be better
From: Borun Fu borun...@intel.com
On VLV, after i915_pm_suspend display power wells are staying
power ungated. So, after initiating mem sleep echo mem /sys/power/state
Display is staing D0 State. There might be better way/place to power gate
these wells. Also, we need to make sure that if wells
