On Tue, Sep 24, 2019 at 4:21 PM Souza, Jose wrote:
>
> On Tue, 2019-09-24 at 16:00 +0300, Imre Deak wrote:
> > On Mon, Sep 23, 2019 at 03:02:54PM -0700, Lucas De Marchi wrote:
> One odd thing that I notice is that we use port instead of tc_port in
> most MG registers, those MG registers uses a
On Wed, Sep 25, 2019 at 02:21:52AM +0300, Souza, Jose wrote:
> On Tue, 2019-09-24 at 16:00 +0300, Imre Deak wrote:
> > On Mon, Sep 23, 2019 at 03:02:54PM -0700, Lucas De Marchi wrote:
> > > On Mon, Sep 23, 2019 at 12:55 PM José Roberto de Souza
> > > wrote:
> > > > [...]
> > > > +
On Tue, 2019-09-24 at 16:00 +0300, Imre Deak wrote:
> On Mon, Sep 23, 2019 at 03:02:54PM -0700, Lucas De Marchi wrote:
> > On Mon, Sep 23, 2019 at 12:55 PM José Roberto de Souza
> > wrote:
> > > [...]
> > > + ln1 &= ~(DKL_DP_MODE_CFG_DP_X1_MODE |
> > > DKL_DP_MODE_CFG_DP_X2_MODE);
>
On Mon, Sep 23, 2019 at 03:02:54PM -0700, Lucas De Marchi wrote:
> On Mon, Sep 23, 2019 at 12:55 PM José Roberto de Souza
> wrote:
> > [...]
>
> > + ln1 &= ~(DKL_DP_MODE_CFG_DP_X1_MODE |
> > DKL_DP_MODE_CFG_DP_X2_MODE);
> > +
> > + lane_mask =
On Mon, Sep 23, 2019 at 12:55 PM José Roberto de Souza
wrote:
>
> From: Clinton A Taylor
>
> Added DKL Phy sequences and helpers functions to program voltage
> swing, clock gating and dp mode.
>
> It is not written in DP enabling sequence but "PHY Clockgating
> programming" states that clock
