mark update need to wait for next VSYNC?
On Sun, Sep 06, 2015 at 07:30:26PM +0800, Zhi Wang wrote:
> Hi William:
> There is a kind of display register marked as double-buffered. It
> means that HW will *not* latch the value in the register all the time.
> HW will only lat
Hi William:
There is a kind of display register marked as double-buffered. It
means that HW will *not* latch the value in the register all the time.
HW will only latch the value on the start of the vertical blank, or the
time when pipe/plane are enabling.
So you will see some code pieces
On Sun, Sep 06, 2015 at 07:30:26PM +0800, Zhi Wang wrote:
> Hi William:
> There is a kind of display register marked as double-buffered. It
> means that HW will *not* latch the value in the register all the time.
> HW will only latch the value on the start of the vertical blank, or the
>
Thanks Ville! Learned from you guys. :)
于 09/06/15 19:50, Ville Syrjälä 写道:
On Sun, Sep 06, 2015 at 07:30:26PM +0800, Zhi Wang wrote:
Hi William:
There is a kind of display register marked as double-buffered. It
means that HW will *not* latch the value in the register all the time.
HW
