[Intel-gfx] [PATCH 0/4] gtt cache coherency checker for i830 class hw

Hi all, This is part of my try-to-fix-i855-cache-coherency patch. It's essentially everything save the actual hacks to fix the gtt chipset flush (that simply not yet ready). The most important part is the cache coherency checker. I think merging this without any other fixes is worth it for a few

[Intel-gfx] [PATCH 1/4] agp/intel-gtt: steal the last gtt page

This page will be used to check cache coherency on i8xx chips. Furthermore gem in drm/i915 doesn't use the last page in the gtt already to prevent pagefaults due to the gpu prefetcher crossing into unmapped memory. So this page is useless, anyway. This introduces include/drm/intel-gtt.h. Atm it

[Intel-gfx] [PATCH 2/4] drm/i915: add locking around chipset flush

My cache coherency checker for i8xx chipsets will make cache flushes stateful. Therefore add some locking around the only caller that had none. This is not a fast-path, anyway, so it won't hurt for the other chipsets. Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch ---

[Intel-gfx] [PATCH 4/4] agp/intel-gtt: extract mch buffer flush in i830 chipset flush

Just a small clean up. The real fix will add tons of code here, so it's nice to shrink the function a tad bit, first. Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch --- drivers/char/agp/intel-gtt.c | 24 1 files changed, 16 insertions(+), 8 deletions(-) diff

[Intel-gfx] [PATCH] drm/i915: Mark the object as dirty when setting to the CPU write domain.

Or else we may not write back the written pages upon unbind. For example the contents of a batch buffer written using a simple mmap or using shmmem pwrite may be discarded if we are forced to evict everything whilst pinning the objects for execbuffer. Signed-off-by: Chris Wilson