Re: [Intel-gfx] [PATCH 0/3] implement multiple ring buffer V1

2010-05-20 Thread Zou, Nanhai
-Original Message- From: Daniel Vetter [mailto:dan...@ffwll.ch] Sent: 2010年5月20日 1:26 To: Zou, Nanhai Cc: intel-gfx; Anholt, Eric; Xiang, Haihao Subject: Re: [Intel-gfx] [PATCH 0/3] implement multiple ring buffer V1 On Wed, May 19, 2010 at 05:33:28PM +0800, Zou Nan hai wrote: The patch

Re: [Intel-gfx] [PATCH 0/3] implement multiple ring buffer V1

2010-05-20 Thread Daniel Vetter
On Thu, May 20, 2010 at 03:38:13PM +0800, Zou, Nanhai wrote: Thanks for the hints, I was using git format-patch and git-send-email to send out those patches. Hmm, that's strange. I've checked my ~/.gitconfig and there is nothing in there to enable automagic threading - it Just Works

[Intel-gfx] [PATCH 1/2] IPS driver: add GPU busy and turbo checking

2010-05-20 Thread Jesse Barnes
Be sure to enable GPU turbo by default at load time and check GPU busy and MCP exceeded status correctly. Also fix up CPU power comparison and work around buggy MCH temp reporting. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/platform/x86/intel_ips.c | 30

[Intel-gfx] [PATCH 2/2] drm/i915: add power monitoring support

2010-05-20 Thread Jesse Barnes
Add power monitoring support to the i915 driver for use by the IPS driver. Export the available power info to the IPS driver through a few new inter-driver hooks. When used together, the IPS driver and this patch can significantly increase graphics performance on Ironlake class chips.

Re: [Intel-gfx] Picture quality on laptop LCD with i915GM chipset

2010-05-20 Thread SD
From: Jin, Gordon gordon.jin at intel.com Subject: RE: [Intel-gfx] Picture quality on laptop LCD with i915GM chipset To: SD sd.domrep at yahoo.com, intel-gfx at lists.freedesktop.org intel-gfx at lists.freedesktop.org Date: Wednesday, May 19, 2010, 6:03 AM SD wrote on Wednesday, May 19,

[Intel-gfx] [PATCH 0/3] implement multiple ring buffer V2

2010-05-20 Thread Zou Nan hai
The patch series try to abstruct ring buffer structure, implement BSD (bit stream decoder) ring buffer for H.264/VC1 VLD decoding. previous version has regression on legacy platform. fixed in this version ___ Intel-gfx mailing list

[Intel-gfx] [PATCH 3/3] implement BSD ring buffer V2

2010-05-20 Thread Zou Nan hai
implement BSD (bit stream decoder) ring buffer for H.264/VC1 VLD decoding on G45+ Signed-off-by: Zou Nan hai nanhai@intel.com Signed-off-by: Xiang Hai hao haihao.xi...@intel.com --- drivers/gpu/drm/i915/i915_dma.c |2 + drivers/gpu/drm/i915/i915_drv.h |2 +

Re: [Intel-gfx] [PATCH] drm/i915: Fix PIPE_CONTROL command on Sandybridge

2010-05-20 Thread Zhenyu Wang
On 2010.05.14 10:53:50 +0800, Zhenyu Wang wrote: I tried to test this with noop request and issue PIPE_CONTROL command for each sequence and track notify interrupts, which seems work fine. Hopefully we don't need workaround like on Ironlake for Sandybridge. oh, I've another patch which