Unfortunately Android threads do not support cancel and testcancel, so this
Test cannot build for android.
Do we really need a cancellation point, since we don't need to cancel the
thread.
Tvrtko's original solution seemed workable, if a bit less polished.
Tim
-Original Message-
On 07/18/2014 10:20 AM, Gore, Tim wrote:
Unfortunately Android threads do not support cancel and testcancel, so this
Test cannot build for android.
Do we really need a cancellation point, since we don't need to cancel the
thread.
Tvrtko's original solution seemed workable, if a bit less
On 7/17/2014 5:25 PM, Chris Wilson wrote:
On Wed, Jul 16, 2014 at 05:22:38PM +0100, daniele.ceraolospu...@intel.com wrote:
From: Daniele Ceraolo Spurio daniele.ceraolospu...@intel.com
The context used to execute a batchbuffer is becoming increasingly
important. Duplicating to avoid
On Thu, Jul 17, 2014 at 02:31:14PM -0700, Ben Widawsky wrote:
- for_each_ring(useless, dev_priv, i) {
+ for_each_ring(to, dev_priv, i) {
u16 signal_offset =
(GEN8_SIGNAL_OFFSET(ring, i) PAGE_MASK) / 4;
u32 *tmp =
On Fri, Jul 18, 2014 at 11:04:03AM +0530, sonika.jin...@intel.com wrote:
From: Sonika Jindal sonika.jin...@intel.com
This series prepares future platform enabling by changing HAS_PCH_SPLIT to
more
appropriate check since the code accessed may not have anything to do with
having PCH or not.
On 7/18/2014 4:26 PM, Damien Lespiau wrote:
On Fri, Jul 18, 2014 at 11:04:03AM +0530, sonika.jin...@intel.com wrote:
From: Sonika Jindal sonika.jin...@intel.com
This series prepares future platform enabling by changing HAS_PCH_SPLIT to more
appropriate check since the code accessed may not
On Fri, Jul 18, 2014 at 1:16 AM, Ben Widawsky b...@bwidawsk.net wrote:
On Fri, Jul 11, 2014 at 10:20:08AM -0700, armin.c.re...@intel.com wrote:
From: Armin Reese armin.c.re...@intel.com
Signed-off-by: Armin Reese armin.c.re...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 13
On Fri, Jul 18, 2014 at 04:53:34PM +0530, Jindal, Sonika wrote:
On 7/18/2014 4:26 PM, Damien Lespiau wrote:
On Fri, Jul 18, 2014 at 11:04:03AM +0530, sonika.jin...@intel.com wrote:
From: Sonika Jindal sonika.jin...@intel.com
This series prepares future platform enabling by changing
On Thu, Jul 17, 2014 at 04:45:02PM -0700, Ben Widawsky wrote:
On Fri, Jul 11, 2014 at 10:20:07AM -0700, armin.c.re...@intel.com wrote:
From: Armin Reese armin.c.re...@intel.com
Signed-off-by: Armin Reese armin.c.re...@intel.com
---
drivers/gpu/drm/i915/i915_gem.c | 6 +++---
1 file
On Fri, Jul 18, 2014 at 10:43:36AM +0100, Ceraolo Spurio, Daniele wrote:
On 7/17/2014 5:25 PM, Chris Wilson wrote:
On Wed, Jul 16, 2014 at 05:22:38PM +0100, daniele.ceraolospu...@intel.com
wrote:
From: Daniele Ceraolo Spurio daniele.ceraolospu...@intel.com
The context used to execute a
On Thu, Jul 17, 2014 at 10:31:30PM +0200, Jan Niggemann wrote:
Hi list,
you were very helpful to nail down the interrupt storm issue a year ago, I
hope we can track this down, too.
I'm experiencing an issue with 3.15.5 on my Lenovo T400:
When my machine boots, I can see some of the boot
On Fri, Jul 18, 2014 at 02:04:56PM +0100, Damien Lespiau wrote:
On Fri, Jul 18, 2014 at 04:53:34PM +0530, Jindal, Sonika wrote:
On 7/18/2014 4:26 PM, Damien Lespiau wrote:
On Fri, Jul 18, 2014 at 11:04:03AM +0530, sonika.jin...@intel.com wrote:
From: Sonika Jindal
After unclaimed register detection was enabled for BDW, I started seeing
warnings while reading registers 0x4400c (DEIER) and 0x4401c (GTIER).
From Gen8, DEIER has been split per display engine pipe, and GTIER has
been split in 4.
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
On Thu, Jul 17, 2014 at 05:37:12PM +, Kay, Allen M wrote:
That sounds great. Tiejun could you confirm that with windows driver guys
too?
I believe windows driver can also assume specific CPU/PCH combos. I will
discuss this with native Windows driver guys. Preferably, the same code
Hi Daniel,
Am 18.07.2014 15:27, schrieb Daniel Vetter:
On Thu, Jul 17, 2014 at 10:31:30PM +0200, Jan Niggemann wrote:
I'm experiencing an issue with 3.15.5 on my Lenovo T400:
Since 3.15 (or 3.14, can't say for sure), the boot starts normally,
but the
first mode change doesn't occur, resulting
Summary
We covered the platform: Broadwell, Baytrail-M, Haswell (mobile, desktop and
ULT), Ivybridge, SandyBridge, IronLake.
In this circle, 0 new bugs is filed.
Finding
We found four issues as below, but all of them can be fixed by latest -nightly
or latest -fixes . So we didn't file bug.
1)
---
tools/intel_gpu_top.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index b5cfda0..fef7f96 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -711,7 +711,8 @@ int main(int argc, char **argv)
}
The previous sample rate of ~167 per frame was rather low in relation to
frequency of the events being measured and so for example the derived
busy status could become quite unstable at times.
---
tools/intel_gpu_top.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
---
lib/intel_reg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index 8a6e3f1..51430f4 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -671,6 +671,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define RING_NO_REPORT 0x
This register holds more than the length. This also renames the lsb to
RING_ENABLED.
---
lib/intel_reg.h | 7 ++-
tools/intel_gpu_top.c | 2 +-
2 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index 56459ea..8a6e3f1 100644
---
---
lib/instdone.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/lib/instdone.c b/lib/instdone.c
index 99857e2..57b1635 100644
--- a/lib/instdone.c
+++ b/lib/instdone.c
@@ -381,23 +381,23 @@ init_g4x_instdone1(void)
static void
The absolute values of the pipeline statistic counters are more
distracting than they are useful.
---
tools/intel_gpu_top.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index e5582fd..0ef26f8 100644
--- a/tools/intel_gpu_top.c
Since it seemed like a re-occurring complaint that developers didn't feel
they could trust the numbers from intel-gpu-top I reviewed the
implementation and came across a few issues that I've tried to address in
this series.
Just to let others know; I'm also experimenting with the possibility of
---
tools/intel_gpu_top.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 7574ef0..3115b5e 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -39,6 +39,9 @@
#include sys/time.h
#include
---
tools/intel_gpu_top.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index f60e58b..7574ef0 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -344,6 +344,15 @@ static void ring_sample(struct ring *ring)
The pipeline statistics counters represent per context values and so we
can't assume that a snapshot taken once per second will correspond to the
same context as the last snapshot.
We now read the statistics counters for every sample and before and
after each sample we read the current context id
semaphore _sync_seqno, _seqno and _mbox are smaller than number of rings.
This optimization is to remove the ring itself from the list and the logic to
do that
is at intel_ring_sync_index as below:
/*
* rcs - 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
* vcs - 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
On Fri, Jul 18, 2014 at 01:39:29AM -0700, Rodrigo Vivi wrote:
semaphore _sync_seqno, _seqno and _mbox are smaller than number of rings.
This optimization is to remove the ring itself from the list and the logic to
do that
is at intel_ring_sync_index as below:
/*
* rcs - 0 = vcs, 1 = bcs,
semaphore _sync_seqno, _seqno and _mbox are smaller than number of rings.
This optimization is to remove the ring itself from the list and the logic to
do that
is at intel_ring_sync_index as below:
/*
* rcs - 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
* vcs - 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
On Fri, Jul 18, 2014 at 02:05:16AM -0700, Rodrigo Vivi wrote:
semaphore _sync_seqno, _seqno and _mbox are smaller than number of rings.
This optimization is to remove the ring itself from the list and the logic to
do that
is at intel_ring_sync_index as below:
/*
* rcs - 0 = vcs, 1 = bcs,
semaphore _sync_seqno, _seqno and _mbox are smaller than number of rings.
This optimization is to remove the ring itself from the list and the logic to
do that
is at intel_ring_sync_index as below:
/*
* rcs - 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
* vcs - 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
On Fri, Jul 18, 2014 at 4:49 PM, Jan Niggemann j...@hz6.de wrote:
Am 18.07.2014 15:27, schrieb Daniel Vetter:
On Thu, Jul 17, 2014 at 10:31:30PM +0200, Jan Niggemann wrote:
I'm experiencing an issue with 3.15.5 on my Lenovo T400:
Since 3.15 (or 3.14, can't say for sure), the boot starts
Hi Dave,
Oops, missed the -fixes train. But in any case nothing really shocking in
here, 2 reverts, 1 quirk and a regression fix a WARN.
Cheers, Daniel
The following changes since commit 1795cd9b3a91d4b5473c97f491d63892442212ab:
Linux 3.16-rc5 (2014-07-13 14:04:33 -0700)
are available in
Hi Dave,
drm-intel-next-2014-07-11:
- fbc improvements when stolen memory is tight (Ben)
- cdclk handling improvements for vlv/chv (Ville)
- proper fix for stuck primary planes on gmch platforms with cxsr (ImreEbgert
Eich)
- gen8 hw semaphore support (Ben)
- more execlist prep work from Oscar
Hi Dave,
Just flushing out my random drm patches queue. Nothing fancy in here at
all.
Cheers, Daniel
The following changes since commit b957f457fbce30cc4901dc28f2b56f2b15dfe84a:
drm/radeon: use helpers (2014-07-18 14:25:23 +1000)
are available in the git repository at:
Hi Daniel, hi others,
Can you please boot with drm.debug=0xe and grab a new dmesg with the
backtrace?
Ok, thanks for looking into this, and sorry for taking so long. I'm back
now and had now finally some availability to check this issue again with
the latest kernel.
Seems to be fixed,
For the MCH PCI registers that do need to be read - can you tell us which
ones those are?
In qemu/hw/xen_pt_igd.c/igd_pci_read(), following MCH PCI config register reads
are passthrough to the host HW. Some of the registers are needed by Ironlake
GFX driver which we probably can remove. I
On Fri, Jul 18, 2014 at 02:19:40AM -0700, Rodrigo Vivi wrote:
semaphore _sync_seqno, _seqno and _mbox are smaller than number of rings.
This optimization is to remove the ring itself from the list and the logic to
do that
is at intel_ring_sync_index as below:
/*
* rcs - 0 = vcs, 1 = bcs,
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