On Wed, Mar 11, 2015 at 10:52:29AM +0100, Daniel Vetter wrote:
On Tue, Mar 10, 2015 at 07:57:13PM +0200, Ville Syrjälä wrote:
On Tue, Mar 10, 2015 at 10:01:51AM -0700, Matt Roper wrote:
On Tue, Mar 10, 2015 at 01:15:24PM +0200, ville.syrj...@linux.intel.com
wrote:
From: Ville Syrjälä
On Wed, Mar 11, 2015 at 10:52:29AM +0100, Daniel Vetter wrote:
On Tue, Mar 10, 2015 at 07:57:13PM +0200, Ville Syrjälä wrote:
On Tue, Mar 10, 2015 at 10:01:51AM -0700, Matt Roper wrote:
On Tue, Mar 10, 2015 at 01:15:24PM +0200, ville.syrj...@linux.intel.com
wrote:
From: Ville Syrjälä
From: Jeff McGee jeff.mc...@intel.com
New test pm_sseu is intended for any subtest related to the
slice/subslice/EU power gating feature. The sole initial subtest,
'full-enable', confirms that the slice/subslice/EU state is at
full enablement when the render engine is active. Starting with
Gen9
From: Jeff McGee jeff.mc...@intel.com
The media spin utility is derived from media fill. The purpose
is to create a simple means to keep the render engine (media
pipeline) busy for a controlled amount of time. It does so by
emitting a batch with a single execution thread that spins in
a tight
On 03/10/2015 07:16 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Wrap the FW register value shift+mask operations into a macro to hide
the ugliness a bit. Also might avoid bugs due to typos.
Also rename all the primary/sprite plane low order
On Tue, Mar 10, 2015 at 01:58:52PM -0400, Rob Clark wrote:
On Tue, Mar 10, 2015 at 12:59 PM, Jeff McGee jeff.mc...@intel.com wrote:
On Tue, Mar 10, 2015 at 08:37:30AM +0100, Daniel Vetter wrote:
On Mon, Mar 09, 2015 at 04:41:02PM -0700, jeff.mc...@intel.com wrote:
From: Jeff McGee
On Tue, Mar 10, 2015 at 10:13:52AM -0700, Matt Roper wrote:
On Tue, Mar 10, 2015 at 01:15:27PM +0200, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
When enabling planes during .crtc_enable() we currently want to update
the watermarks before
From: Ville Syrjälä ville.syrj...@linux.intel.com
CHV should be in a good enough shape now, so let's drop the
.is_preliminary flag.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 1 -
1 file changed, 1 deletion(-)
diff --git
On Tue, Mar 10, 2015 at 10:10:40AM -0700, Matt Roper wrote:
On Tue, Mar 10, 2015 at 01:15:25PM +0200, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
In preparation to movable/resizable primary planes pass the clipped
plane size to
On Tue, Mar 10, 2015 at 10:01:51AM -0700, Matt Roper wrote:
On Tue, Mar 10, 2015 at 01:15:24PM +0200, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
We need to call the plane .atomic_check() hook when enabling the crtc
to make sure all the derived
On Thu, 12 Mar 2015, Xi Ruoyao xry...@outlook.com wrote:
In intel_crtc_page_flip, intel_display.c, the code changed the framebuffer
assigned to plane crtc-primary by
crtc-primary-fb = fb;
However, it forgot to change crtc-primary-state-fb. However, when we
switch to console, some kernel
Hi Dave -
More i915 fixes, three out of four are fixes to old bugs, cc: stable.
BR,
Jani.
The following changes since commit 9eccca0843205f87c00404b663188b88eb248051:
Linux 4.0-rc3 (2015-03-08 16:09:09 -0700)
are available in the git repository at:
On Wed, Mar 11, 2015 at 09:18:19PM +, Chris Wilson wrote:
Arguably busy-spinning on an idle system isn't totally evil, but it
certainly is likely to come at a power cost. On the other hand, spinning
is relatively rare outside of benchmarks. Rare enough to be useful?
As a counterpoint, I
On Thu, Mar 12, 2015 at 09:35:33AM +0200, Ander Conselvan De Oliveira wrote:
(for the series)
Reviewed-by: Ander Conselvan de Oliveira conselv...@gmail.com
Both merged to dinq, thanks.
-Daniel
On Wed, 2015-03-11 at 18:52 +0200, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
On Wed, Mar 11, 2015 at 09:18:19PM +, Chris Wilson wrote:
On Wed, Mar 11, 2015 at 03:29:19PM +, Chris Wilson wrote:
+ while (!need_resched()) {
+ if (i915_gem_request_completed(req, true)) {
+ ret = 0;
+ goto out;
+ }
+
On Wed, Mar 11, 2015 at 08:20:44PM -0700, Todd Previte wrote:
On 3/11/2015 1:52 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
We accidentally pass 'pipe' instead of 'port' to CHV_PLL_DW8() and
with PIPE_C we end up at register offset 0x8320 which
On Wed, Mar 11, 2015 at 05:23:27PM +0100, Daniel Vetter wrote:
On Wed, Mar 11, 2015 at 02:19:38PM +0200, Ville Syrjälä wrote:
On Wed, Mar 11, 2015 at 11:24:34AM +0100, Daniel Vetter wrote:
On Wed, Mar 11, 2015 at 12:05:39PM +0200, Ville Syrjälä wrote:
On Wed, Mar 11, 2015 at 10:52:29AM
On Wed, Mar 11, 2015 at 02:12:02PM -0700, Jesse Barnes wrote:
On 03/05/2015 09:37 PM, akash.g...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
Enable the RPS interrupts programming(enable/disable/reset) for GEN9,
as missing changes to enable the RPS support on GEN9 have been
On Wed, Mar 11, 2015 at 12:27:59PM -0700, Jesse Barnes wrote:
On 03/05/2015 09:37 PM, akash.g...@intel.com wrote:
+ /* Leaning on the below call to gen6_set_rps to program/setup the
+* Up/Down EI threshold registers, as well as the RP_CONTROL,
+* RP_INTERRUPT_LIMITS RPNSWREQ
On 03/11/2015 12:46 PM, Chris Wilson wrote:
On Wed, Mar 11, 2015 at 12:27:59PM -0700, Jesse Barnes wrote:
On 03/05/2015 09:37 PM, akash.g...@intel.com wrote:
+ /* Leaning on the below call to gen6_set_rps to program/setup the
+* Up/Down EI threshold registers, as well as the RP_CONTROL,
This provides a nice boost to mesa in swap bound scenarios (as mesa
throttles itself to the previous frame and given the scenario that will
complete shortly). It will also provide a good boost to systems running
with semaphores disabled and so frequently waiting on the GPU as it
switches rings. In
Matt, please review or suggest an alternative for v4.0-rc.
Thanks,
Jani.
On Thu, 12 Mar 2015, Xi Ruoyao xry...@outlook.com wrote:
plane-state-fb and plane-fb should always reference the same FB so
that atomic and legacy codepaths have the same view of display state.
However, there are some
plane-state-fb and plane-fb should always reference the same FB so
that atomic and legacy codepaths have the same view of display state.
However, there are some places in kernel code that directly set
plane-fb and neglect to update plane-state-fb. If we never do a
successful update through the
In intel_crtc_page_flip, intel_display.c, the code changed the framebuffer
assigned to plane crtc-primary by
crtc-primary-fb = fb;
However, it forgot to change crtc-primary-state-fb. However, when we
switch to console, some kernel code will read crtc-primary-state-fb
to get the framebuffer
On Fri, Mar 6, 2015 at 5:23 PM, Kumar, Shobhit shobhit.ku...@intel.com wrote:
There are actually two lines for Panel Power control and Backlight
enable/disable. I have already moved towards adding a new Cell device
for PWM child device and a new pwm driver for the same. That will take
care of
On 03/12/2015 04:28 PM, Jani Nikula wrote:
On Thu, 12 Mar 2015, Xi Ruoyao xry...@outlook.com wrote:
In intel_crtc_page_flip, intel_display.c, the code changed the framebuffer
assigned to plane crtc-primary by
crtc-primary-fb = fb;
However, it forgot to change crtc-primary-state-fb. However,
On Tue, Mar 03, 2015 at 02:10:53PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Starting with Skylake the display engine can scan out Y tiled objects. (Both
legacy Y tiled, and the new Yf format.)
This series takes the original work by Damien Lespiau and
Fix the following warning:
igt_fb.c: In function 'igt_create_fb_with_bo_size':
igt_fb.c:414:2: warning: format '%llx' expects argument of type
'long long unsigned int', but argument 9 has type 'uint64_t' [-Wformat=]
igt_debug(%s(width=%d, height=%d, format=0x%x [bpp=%d], tiling=%llx,
In intel_crtc_page_flip, intel_display.c, the code changed the framebuffer
assigned to plane crtc-primary by
crtc-primary-fb = fb;
However, it forgot to change crtc-primary-state-fb. However, when we
switch to console, some kernel code will read crtc-primary-state-fb
to get the framebuffer
On 03/12/2015 11:11 AM, Chris Wilson wrote:
This provides a nice boost to mesa in swap bound scenarios (as mesa
throttles itself to the previous frame and given the scenario that will
complete shortly). It will also provide a good boost to systems running
with semaphores disabled and so
On Wed, Feb 18, 2015 at 1:18 PM, Shobhit Kumar shobhit.ku...@intel.com wrote:
Export Panel BACKLIGHT_EN(offset 0x51) and PANEL_EN(offset 0x52) as two
additional GPIOs. Needed by display driver to enable the DSI panel on
BYT platform where the Panel EN/Disable and Backlight control are
routed
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index
On Thu, Mar 12, 2015 at 01:14:30PM +, Tvrtko Ursulin wrote:
On 03/12/2015 11:11 AM, Chris Wilson wrote:
This provides a nice boost to mesa in swap bound scenarios (as mesa
throttles itself to the previous frame and given the scenario that will
complete shortly). It will also provide a good
On Tue, Jan 20, 2015 at 11:36:03AM +0100, Daniel Vetter wrote:
On Mon, Jan 12, 2015 at 10:21:58AM -0800, Rodrigo Vivi wrote:
Use cmdline variable for interactive debug instead of env var.
v2: Make interactive-debug domain optional and use all when not set.
Signed-off-by: Rodrigo Vivi
igt_interactive_debug should be defined in igt_core.c, rather than the
header, to avoid it being defined more than once.
Reported-by: Damien Lespiau damien.lesp...@intel.com
Signed-off-by: Thomas Wood thomas.w...@intel.com
---
lib/igt_core.c | 1 +
lib/igt_core.h | 2 +-
2 files changed, 2
On Mon, 2015-03-09 at 18:15 +0100, Linus Walleij wrote:
On Fri, Mar 6, 2015 at 5:23 PM, Kumar, Shobhit shobhit.ku...@intel.com
wrote:
There are actually two lines for Panel Power control and Backlight
enable/disable. I have already moved towards adding a new Cell device
for PWM child
From: Ville Syrjälä ville.syrj...@linux.intel.com
Consider the link rates reported by the sink via
DP_SUPPORTED_LINK_RATES when checking modes against the max link
rate.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 15 ++-
From: Ville Syrjälä ville.syrj...@linux.intel.com
TODO: Is there an actually nice way to print an array of ints?
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 43 +
1 file changed, 43 insertions(+)
diff
From: Ville Syrjälä ville.syrj...@linux.intel.com
intel_dp_compute_config() only really needs to know the rates supported
by both source and sink, so hide the raw source and sink arrays from it.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 37
From: Ville Syrjälä ville.syrj...@linux.intel.com
Now that intel_dp_max_link_bw() no longer considers the source
restrictions we may try to enable MST with 5.4GHz even when the source
doesn't support it. To fix that switch the code over to handle the link
rate in the same way as the SST code
From: Ville Syrjälä ville.syrj...@linux.intel.com
Now that both source and sink rates are always filled in there's no need
for any special cases in intel_supported_rates().
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 8
1 file
From: Ville Syrjälä ville.syrj...@linux.intel.com
No point in converting from hardware format every single time, just
store the rates in the final format under intel_dp.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 33
From: Ville Syrjälä ville.syrj...@linux.intel.com
Remove the sink vs. source limit mess from intel_dp_max_link_bw() and
just move the source restriction checks to intel_dp_source_rates().
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 22
On Thu, Mar 12, 2015 at 10:28:56AM +0200, Jani Nikula wrote:
On Thu, 12 Mar 2015, Xi Ruoyao xry...@outlook.com wrote:
In intel_crtc_page_flip, intel_display.c, the code changed the framebuffer
assigned to plane crtc-primary by
crtc-primary-fb = fb;
However, it forgot to change
Needed for PWM control suuported by the PMIC
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot gnu...@gmail.com
Cc: Thierry Reding thierry.red...@gmail.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
On Thu, Mar 12, 2015 at 03:18:01PM +, Tvrtko Ursulin wrote:
On 03/12/2015 01:18 PM, Chris Wilson wrote:
1ms. I was just thinking of doing USECS_PER_SEC / HZ, then realised that
was a jiffie, hence the confusion. At any rate, it is still the minimum
we can trivially wait for (without an
On some BYT PLatform the PWM is controlled using CRC PMIC. Add a lookup
entry for the same to be used by the consumer (Intel GFX)
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot gnu...@gmail.com
Cc: Thierry Reding thierry.red...@gmail.com
From: Ville Syrjälä ville.syrj...@linux.intel.com
We have a bit of a mess with the source vs. sink link rate handling, so I
went ahead and tried to clean it up. So now we keep the source and sink
rates neatly in their own corners and compute the intersection when needed.
I considered storing the
From: Ville Syrjälä ville.syrj...@linux.intel.com
No point in using uint32_t here, just plain old int will do.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff
From: Ville Syrjälä ville.syrj...@linux.intel.com
Drop the gen9 checks from the code and issue DP_LINK_RATE_SET whenever
the sink reports to support it.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 13 +++--
1 file changed, 7
From: Ville Syrjälä ville.syrj...@linux.intel.com
P1273_DPLL_Programming Spreadsheet.xlsm lists a boatload of
frequencies for eDP. Try to use them all.
For now I've decided not to add hardcoded DPLL dividers for these cases
since chv_find_best_dpll() works just fine.
I've not actually tested
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot gnu...@gmail.com
Cc: Thierry Reding thierry.red...@gmail.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 25 +
Hi All,
These patches try to enable panel control as a new GPIO via lookup table
during pmic core driver loading. Code is modifed to use generic gpiod_*
routines which will take care of ownership issues.
Also a new PWM cell device is added to the PMIC MFD. New PWM driver pwm-crc
is used to do
On some Intel SoC platforms, the panel enable/disable signals are
controlled by CRC PMIC. Add those control as a new GPIO in a lookup
table for gpio-crystalcove chip during CRC driver load
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot
Some chips instead of using period_ns and duty_ns can be configured
using the clock divisor and duty percent. Adds an alternative
configuration method for such chips
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot gnu...@gmail.com
Cc:
Export PANEL_EN/DISABLE (offset 0x52) as additional GPIO. Needed
by display driver to enable the DSI panel on BYT platform where
the Panel EN/Disable control is routed thorugh CRC PMIC
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot
From: Ville Syrjälä ville.syrj...@linux.intel.com
Complain loudly if we ever attempt to overflow the the supported_rates[]
array. This should never happen since the sink_rates[] array will always
be smaller or of equal size. But should someone change that we want to
catch it without scribblign
From: Ville Syrjälä ville.syrj...@linux.intel.com
The source rates don't change, so we can just point the caller at the
const arrays.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 24 ++--
1 file changed, 10 insertions(+),
On 03/12/2015 01:18 PM, Chris Wilson wrote:
On Thu, Mar 12, 2015 at 01:14:30PM +, Tvrtko Ursulin wrote:
On 03/12/2015 11:11 AM, Chris Wilson wrote:
This provides a nice boost to mesa in swap bound scenarios (as mesa
throttles itself to the previous frame and given the scenario that will
On Thu, Mar 12, 2015 at 02:45:31PM +0200, Jani Nikula wrote:
Matt, please review or suggest an alternative for v4.0-rc.
Thanks,
Jani.
Yep, this looks good to me. So
Reviewed-by: Matt Roper matthew.d.ro...@intel.com
Matt
On Thu, 12 Mar 2015, Xi Ruoyao xry...@outlook.com wrote:
On Thu, Mar 12, 2015 at 04:41:10PM +, Tvrtko Ursulin wrote:
Yes I didn't mean that - but to have a boolean spinning-wait=on/off.
Maybe default to on on HZ=1000 with preemption, or the opposite,
something like that.
I don't see the point in having the complication, until someone
complains.
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5940
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -6 274/274
A new intel-gpu-tools quarterly release is available with the following changes:
- New frequency manipulation tool (intel_gpu_frequency)
- Adjustments for the Solaris port (Alan Coopersmith).
- Remove tests/NAMING-CONVENTION since it's all in the docbook now, to avoid
divergent conventions.
On 03/12/2015 04:50 PM, Chris Wilson wrote:
On Thu, Mar 12, 2015 at 04:41:10PM +, Tvrtko Ursulin wrote:
Yes I didn't mean that - but to have a boolean spinning-wait=on/off.
Maybe default to on on HZ=1000 with preemption, or the opposite,
something like that.
I don't see the point in
From: Jeff McGee jeff.mc...@intel.com
New test pm_sseu is intended for any subtest related to the
slice/subslice/EU power gating feature. The sole initial subtest,
'full-enable', confirms that the slice/subslice/EU state is at
full enablement when the render engine is active. Starting with
Gen9
From: Jeff McGee jeff.mc...@intel.com
New test core_getparams consists of 2 subtests, each one testing
the ability of userspace to query the correct value of a GT config
attribute: subslice total or EU total. drm/i915 implementation of
these queries is required for Cherryview and Gen9+ devices
On Thu, Mar 12, 2015 at 10:08:54AM +0800, Zhigang Gong wrote:
LGTM,
Reviewed-by: Zhigang Gong zhigang.g...@linux.intel.com
Thanks.
Thanks for the review, Zhigang.
With beignet portion reviewed, review should be able to proceed for
the i915, libdrm, and igt parts. These are all quite
From: Ville Syrjälä ville.syrj...@linux.intel.com
Once we've read the rates from the sink we don't have to mess with them,
so the caller can just look at the stored rates without doing extra
copies. If the sink doesn't support the new link rate stuff, we just
point the caller at the
The Crystalcove PMIC controls PWM signals and this driver exports that
capability as a PWM chip driver. This is platform device implementtaion
of the drivers/mfd cell device for CRC PMIC
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot
The CRC (Crystal Cove) PMIC, controls the panel enable and disable
signals for BYT for dsi panels. This is indicated in the VBT fields. Use
that to initialize and use GPIO based control for these signals.
v2: Use the newer gpiod interface(Alexandre)
CC: Samuel Ortiz sa...@linux.intel.com
Cc:
For platforms where there are DT, some early MFD modules can reguster
lookup tables. Remove __init initializer so that this works. This is
similar to gpio_add_lookup_table which allows later initializations
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc:
On 02/11/2015 09:43 AM, Damien Lespiau wrote:
v2: Use the recently introduced INTEL_REVID() and SKL_REVID defines
(Nick Hoath)
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff
On Thu, 12 Mar 2015, Jesse Barnes jbar...@virtuousgeek.org wrote:
On 02/11/2015 09:43 AM, Damien Lespiau wrote:
v2: Use the recently introduced INTEL_REVID() and SKL_REVID defines
(Nick Hoath)
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c |
From: Jeff McGee jeff.mc...@intel.com
New test core_getparams consists of 2 subtests, each one testing
the ability of userspace to query the correct value of a GT config
attribute: subslice total or EU total. drm/i915 implementation of
these queries is required for Cherryview and Gen9+ devices
On 03/05/2015 09:37 PM, akash.g...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
This patch series add the missing changes, required for proper
functioning of the Turbo feature on SKL. Most of the changes are
mainly due to the fact that on SKL, the frequency has to be programmed
in
On Wed, Mar 11, 2015 at 10:52:28PM +0200, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
CHV should be in a good enough shape now, so let's drop the
.is_preliminary flag.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Yay! Queued for
Same as
commit c883ef1b1c998d2d66866772fd0fc34afa45641e
Author: Mika Kuoppala m...@iki.fi
Date: Tue Oct 28 17:32:30 2014 +0200
drm/i915: Redefine WARN_ON to include the condition
but for WARN_ON_ONCE. Since the kernel WARN_ON_ONCE actually picks up
*our* version of WARN_ON, we end up with
On Mon, 2015-03-09 at 16:19 -0700, Matt Roper wrote:
On Wed, Mar 04, 2015 at 04:33:17PM +0100, Daniel Vetter wrote:
On Tue, Mar 03, 2015 at 03:21:59PM +0200, Ander Conselvan de Oliveira wrote:
For the atomic conversion, the mode set paths need to be changed to rely
on an atomic state
On Thu, Mar 12, 2015 at 11:11:17AM +, Chris Wilson wrote:
This provides a nice boost to mesa in swap bound scenarios (as mesa
throttles itself to the previous frame and given the scenario that will
complete shortly). It will also provide a good boost to systems running
with semaphores
On 10 March 2015 at 21:17, jeff.mc...@intel.com wrote:
From: Jeff McGee jeff.mc...@intel.com
New test pm_sseu is intended for any subtest related to the
slice/subslice/EU power gating feature. The sole initial subtest,
'full-enable', confirms that the slice/subslice/EU state is at
full
Hi,
Much more likeable in general, some comments inline:
On 03/12/2015 11:10 AM, Joonas Lahtinen wrote:
GGTT views are only applicable when dealing with GGTT. Change the code to
reject ggtt_view where it should not be used and require it when it should
be.
v2:
- Dropped _ppgtt_ infixes,
GGTT views are only applicable when dealing with GGTT. Change the code to
reject ggtt_view where it should not be used and require it when it should
be.
v2:
- Dropped _ppgtt_ infixes, allow both types to be passed
- Disregard other but normal views when no view is specified
- More checks that
On 03/10/2015 04:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
No need to go dig throguh intel_crtc-base.cursor when we already have
the same thing as 'plane' local variable.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
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On Wed, 2015-03-11 at 18:52 +0200, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
So these on top of Ander's latest FDI bifurcation patch [1] should hopefully
result in something sane. Didn't test them though, but assuming Ander
has that test somewhere
On Wed, Mar 11, 2015 at 10:41:30AM +0100, Daniel Vetter wrote:
On Tue, Mar 10, 2015 at 07:48:39PM +0200, Ville Syrjälä wrote:
On Tue, Mar 10, 2015 at 10:01:47AM -0700, Matt Roper wrote:
On Tue, Mar 10, 2015 at 01:15:23PM +0200, ville.syrj...@linux.intel.com
wrote:
From: Ville Syrjälä
On Tue, Mar 10, 2015 at 01:15:29PM +0200, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
When the sprite is covering the entire pipe (and color keying is not
enabled) we currently try to automagically disable the primary plane
which is fully covered by
On Friday 06 March 2015 10:10 PM, Daniel Vetter wrote:
On Thu, Mar 05, 2015 at 09:27:59PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
In normal cases, RC6 promotion timer is 1700us/500us. This will
result in more time spent in C1 state. For more residency
(for the series)
Reviewed-by: Ander Conselvan de Oliveira conselv...@gmail.com
On Wed, 2015-03-11 at 18:52 +0200, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Ignore the current state of the pipe and just check crtc_state-enable
and the number of FDI
On Tue, Mar 10, 2015 at 01:15:25PM +0200, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
In preparation to movable/resizable primary planes pass the clipped
plane size to .update_primary_plane().
Personally I feel like it would make more sense to just
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