-Original Message-
From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
Sent: Wednesday, June 03, 2015 12:02 AM
To: Konduru, Chandra; Roper, Matthew D
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 08/24] drm/i915: Do not add planes from
@@ -560,6 +560,49 @@ static bool hdmi_sink_is_deep_color(struct
drm_encoder *encoder)
return false;
}
+/*
+ * Determine if default_phase=1 can be indicated in the GCP
infoframe.
+ *
+ * From HDMI specification 1.4a:
+ * - The first
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
ville.syrj...@linux.intel.com
Sent: Tuesday, May 05, 2015 7:06 AM
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 5/9] drm/i915: Fix 12bpc HDMI enable for IBX
On Tue, May 5, 2015 at 4:30 AM, akash.g...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
Read the efficient frequency (aka RPe) value through the the mailbox
command (0x1A) from the pcode, as done on Haswell and Broadwell.
The turbo minimum frequency softlimit is not revised as per
On Tue, May 12, 2015 at 12:49 AM, akash.g...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
Updated the i915_ring_freq_table debugfs function to allow read of ring
frequency table through Punit interface, for SKL also.
Signed-off-by: Akash Goel akash.g...@intel.com
---
On Wed, Jun 03, 2015 at 12:32:43PM -0700, Konduru, Chandra wrote:
-Original Message-
From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
Sent: Wednesday, June 03, 2015 12:02 AM
To: Konduru, Chandra; Roper, Matthew D
Cc: intel-gfx@lists.freedesktop.org
04 is the minor version. API version is ver1.
So let's follow same scheme used on published version at 01.org.
If really needed the minor version a follow-up updated will be
done. But for now we need to move fwd and unblock end users.
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
On Tue, May 5, 2015 at 4:30 AM, akash.g...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
Ring frequency table programming changes for SKL. No need for a
floor on ring frequency, as the issue of performance impact with
ring running below DDR frequency, is believed to be fixed on SKL
Currently we just disable the GCP infoframe when turning off the port.
That means if the same transcoder is used on a DP port next, we might
end up pushing infoframes over DP, which isn't intended. Just disable
Wonder how it is working. May be it is ok, or never hit using a
On 29/05/2015 17:43, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The seqno value cannot always be used when debugging issues via trace
points. This is because it can be reset back to start, especially
during TDR type tests. Also, when the scheduler arrives the
On 5/22/2015 6:05 PM, Mika Kuoppala wrote:
Make paging structure type agnostic *_px macros to access
page dma struct, the backing page and the dma address.
This makes the code less cluttered on internals of
i915_page_dma.
v2: Superfluous const - nonconst removed
Signed-off-by: Mika Kuoppala
3.10-stable review patch. If anyone has any objections, please let me know.
--
From: =?UTF-8?q?Jan-Simon=20M=C3=B6ller?= dl...@gmx.de
commit 8f375e10ee47b9d7b9b3aefcf67854c6e92708be upstream.
Description:
intel_gmbus_is_forced_bit is no extern as its body is right below.
On Tue, Jun 02, 2015 at 03:37:37PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
MI_MODE is saved in the logical context so WaDisableAsyncFlipPerfMode
must be applied using LRIs on gen8.
Signed-off-by: Ville Syrjälä
On 29/05/2015 17:44, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
In _i915_add_request(), the request is associated with a userland client.
Specifically it is linked to the 'file' structure and the current user process
is recorded. One problem here is that the
On Wed, 03 Jun 2015 09:49:43 +0300
Jani Nikula jani.nik...@linux.intel.com wrote:
On Wed, 03 Jun 2015, Ben Widawsky benjamin.widaw...@intel.com wrote:
in
commit 65ca7514e21adbee25b8175fc909759c735d00ff
Author: Damien Lespiau damien.lesp...@intel.com
Date: Mon Feb 9 19:33:22 2015 +
On 03/06/2015 00:02, Widawsky, Benjamin wrote:
Probably should have a line like:
Problem introduced in:
instead of just 'in'
in
commit 65ca7514e21adbee25b8175fc909759c735d00ff
Author: Damien Lespiau damien.lesp...@intel.com
Date: Mon Feb 9 19:33:22 2015 +
drm/i915/skl: Implement
From: Tim Gore tim.g...@intel.com
Function check_gpu_ok checks to make sure that any hangs
have cleared by testing for (flags == 0). Some tests set
the STOP_RINGS_ALLOW_BAN and STOP_RINGS_ALLOW_ERRORS flags
but these do not get cleared by an individual ring reset,
(a feature added recently to the
On 5/22/2015 6:05 PM, Mika Kuoppala wrote:
As there is flushing involved when we have done the cpu
write, make functions for mapping for cpu space. Make macros
to map any type of paging structure.
v2: Make it clear tha flushing kunmap is only for ppgtt (Ville)
Cc: Ville Syrjälä
On Tue, Jun 02, 2015 at 03:37:36PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
INSTPM is saved in the logical context so we should initialize it using
LRIs on gen8. It actually defaults to 1 starting from HSW, but let's
keep the write around
On Wed, 03 Jun 2015, Kannan, Vandana vandana.kan...@intel.com wrote:
On 5/26/2015 5:50 PM, Sonika Jindal wrote:
BXT supports following intermediate link rates for edp:
2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
Adding support for programming the intermediate rates.
v2: Adding clock in bxt_clk_div
On Tue, Jun 02, 2015 at 06:21:59PM +, Konduru, Chandra wrote:
@@ -560,6 +560,49 @@ static bool hdmi_sink_is_deep_color(struct
drm_encoder *encoder)
return false;
}
+/*
+ * Determine if default_phase=1 can be indicated in the GCP infoframe.
+ *
+ *
Please help review this patch.
- Vandana
On 5/13/2015 2:52 PM, Kannan, Vandana wrote:
On 5/13/2015 3:13 PM, Vandana Kannan wrote:
Changes for BXT - added a IS_BROXTON check to use the macro related to PPS
registers for BXT.
BXT does not have PP_DIV register. Making changes to handle this.
On Wed, Jun 03, 2015 at 09:20:21AM +0100, tim.g...@intel.com wrote:
From: Tim Gore tim.g...@intel.com
Function check_gpu_ok checks to make sure that any hangs
have cleared by testing for (flags == 0). Some tests set
the STOP_RINGS_ALLOW_BAN and STOP_RINGS_ALLOW_ERRORS flags
but these do not
-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
Sent: Wednesday, June 03, 2015 9:30 AM
To: Gore, Tim
Cc: intel-gfx@lists.freedesktop.org; Wood, Thomas
Subject: Re: [Intel-gfx] [PATCH i-g-t] tests/gem_reset_stats : mask off
ring_stop bits
On Wed, Jun 03,
On Tue, 02 Jun 2015, Damien Lespiau damien.lesp...@intel.com wrote:
On Tue, Jun 02, 2015 at 03:37:35PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
commit 65ca7514e21adbee25b8175fc909759c735d00ff
Author: Damien Lespiau
+intel-gfx, anyone up for a backport?
BR,
Jani.
On Wed, 03 Jun 2015, gre...@linuxfoundation.org wrote:
The patch below does not apply to the 4.0-stable tree.
If someone wants it applied there, or to any other stable or longterm
tree, then please email the backport, including the original git
Op 03-06-15 om 03:27 schreef Matt Roper:
On Mon, Jun 01, 2015 at 03:27:07PM +0200, Maarten Lankhorst wrote:
Use for_each_crtc_state to only touch affected crtc's.
In order to make sure that the initial power is still set
correctly we make sure modeset_update_crtc_power_domains is called
Op 03-06-15 om 03:52 schreef Konduru, Chandra:
-Original Message-
From: Roper, Matthew D
Sent: Tuesday, June 02, 2015 6:30 PM
To: Maarten Lankhorst
Cc: intel-gfx@lists.freedesktop.org; Konduru, Chandra
Subject: Re: [Intel-gfx] [PATCH 08/24] drm/i915: Do not add planes from
On Wed, 03 Jun 2015, Nick Hoath nicholas.ho...@intel.com wrote:
On 03/06/2015 00:02, Widawsky, Benjamin wrote:
Probably should have a line like:
Problem introduced in:
instead of just 'in'
in
commit 65ca7514e21adbee25b8175fc909759c735d00ff
Author: Damien Lespiau damien.lesp...@intel.com
On Tue, 2015-06-02 at 18:17 +0300, Jani Nikula wrote:
On Tue, 02 Jun 2015, Mika Kahola mika.kah...@intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Rather that extracting the current cdclk freuqncy every time someone
wants to know it, cache the current value and use
Op 03-06-15 om 03:28 schreef Matt Roper:
On Mon, Jun 01, 2015 at 03:27:10PM +0200, Maarten Lankhorst wrote:
Move the check for encoder cloning here.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_atomic.c | 5 +-
On Tue, Jun 02, 2015 at 06:18:16PM +, Konduru, Chandra wrote:
-Original Message-
From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
Sent: Tuesday, June 02, 2015 4:11 AM
To: Konduru, Chandra
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2
On Wed, 03 Jun 2015, Damien Lespiau damien.lesp...@intel.com wrote:
On Tue, Jun 02, 2015 at 03:37:37PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
MI_MODE is saved in the logical context so WaDisableAsyncFlipPerfMode
must be applied using
On 5/22/2015 6:05 PM, Mika Kuoppala wrote:
Dynamic page table allocation might wake the shrinker
when memory is requested for page table structures.
As this happens when we try to allocate the virtual address
during binding, our vma might be among the targets for eviction.
We should do
On 5/22/2015 6:05 PM, Mika Kuoppala wrote:
During review of dynamic page tables series, I was able
to hit a lite restore bug with execlists. I assume that
due to incorrect pd, the batch run out of legit address space
and into the scratch page area. The ACTHD was increasing
due to scratch being
Hi Daniel,
Thanks for the review.
Please find my comments inline.
Regards
Shashank
On 6/2/2015 5:23 PM, Daniel Stone wrote:
Hi,
On 2 June 2015 at 12:38, Jindal, Sonika sonika.jin...@intel.com wrote:
On 6/2/2015 1:22 AM, Kausal Malladi wrote:
+int drm_mode_crtc_update_color_property(struct
On Wed, Jun 03, 2015 at 03:43:32PM +0200, Lukas Wunner wrote:
Hi,
a deadlock was introduced by commit 60a5ca015ffd2aacfe5674b5a401cd2a37159e07
Author: Ville Syrjälä ville.syrj...@linux.intel.com
Date: Fri Jun 13 11:10:53 2014 +0300
drm/i915: Add locking around
On 5/22/2015 6:05 PM, Mika Kuoppala wrote:
Write page directory entry without using superfluous
indirect function. Also remove unused device parameter
from the encode function.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
Reviewed-by: Michel Thierry michel.thie...@intel.com
---
Thanks for the review Sonika,
We will incorporate the review comments and send the updated patch set soon.
Regards
Shashank
-Original Message-
From: Jindal, Sonika
Sent: Tuesday, June 02, 2015 5:08 PM
To: Malladi, Kausal; Roper, Matthew D; Barnes, Jesse; Lespiau, Damien; R,
From: Ville Syrjälä ville.syrj...@linux.intel.com
Rather than reading out the current cdclk value use the cached value we
have tucked away in dev_priv.
v2: Rebased to the latest
v3: Rebased to the latest
v4: Fix for patch style problems
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
From: Ville Syrjälä ville.syrj...@linux.intel.com
Bspec says we shouldn't enable IPS on BDW when the pipe pixel rate
exceeds 95% of the core display clock. Apparently this can cause
underruns.
There's no similar restriction listed for HSW, so leave that one alone
for now.
v2: Add
From: Ville Syrjälä ville.syrj...@linux.intel.com
We need to tell BDW ULT and ULX apart.
v2: Rebased to the latest
v3: Rebased to the latest
v4: Fix for patch style problems
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Mika Kahola mika.kah...@intel.com
Author:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Implement support for changing the cdclk frequency during runtime on
HSW. VLV/CHV already have support for this, so we can follow their
example for the most part. Only the actual hardware programming differs,
the rest is pretty much the same.
The
From: Ville Syrjälä ville.syrj...@linux.intel.com
Keep the cdclk maximum supported frequency around in dev_priv so that we
can verify certain things against it before actually changing the cdclk
frequency.
For now only VLV/CHV have support changing cdclk frequency, so other
plarforms get to
Hi,
a deadlock was introduced by commit 60a5ca015ffd2aacfe5674b5a401cd2a37159e07
Author: Ville Syrjälä ville.syrj...@linux.intel.com
Date: Fri Jun 13 11:10:53 2014 +0300
drm/i915: Add locking around framebuffer_references--
The commit amended
On Thu, May 28, 2015 at 11:06:57AM -0300, Paulo Zanoni wrote:
2015-05-28 4:51 GMT-03:00 Daniel Vetter dan...@ffwll.ch:
On Wed, May 27, 2015 at 03:40:32PM -0300, Paulo Zanoni wrote:
2015-05-07 14:38 GMT-03:00 Damien Lespiau damien.lesp...@intel.com:
We now have a special macro for those
From: Ville Syrjälä ville.syrj...@linux.intel.com
Rather that extracting the current cdclk freuqncy every time someone
wants to know it, cache the current value and use that. VLV/CHV already
stored a cached value there so just expand that to cover all platforms.
v2: Rebased to the latest
v3:
This patch series rebases Ville's original cdclk patch series
excluding the ones that has already been reviewed.
http://lists.freedesktop.org/archives/intel-gfx/2014-November/055633.html
The patches are rebased to the latest drm-intel-nightly. The major change
to the original series is the patch
From: Ville Syrjälä ville.syrj...@linux.intel.com
ilk_get_aux_clock_divider() is now a subset of
hsw_get_aux_clock_divider() so unify them.
v2: Rebased to the latest
v3: Rebased to the latest
v4: Fix for patch style problems
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
On 5/22/2015 6:05 PM, Mika Kuoppala wrote:
Lay out scratch page structure in similar manner than other
paging structures. This allows us to use the same tools for
setup and teardown.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 89
On Tue, Jun 02, 2015 at 08:06:59PM +0100, Arun Siluvery wrote:
After GPU reset, HW is losing the address of HWS page in the register.
The page itself is valid except that HW is not aware of its location.
[ 64.368623] [drm:gen8_init_common_ring [i915]] *ERROR* HWS Page address =
0x
On 5/22/2015 6:05 PM, Mika Kuoppala wrote:
Scratch page is part of i915_address_space due to that we
have only one of that. Move other scratch entities into
the same struct. This is a preparatory patch for having
only one instance of each scratch_pt/pd.
Signed-off-by: Mika Kuoppala
On 5/22/2015 6:05 PM, Mika Kuoppala wrote:
Introduce base page handling functions in order of
alloc, free, init. No functional changes.
Can you change this sentence like this?
_Keep/Maintain_ base page handling functions in order of
alloc, free and init. No functional changes.
On 5/22/2015 6:05 PM, Mika Kuoppala wrote:
As we use one scratch page for all ppgtt instances, we can
use one scratch page table and scratch directory across
all ppgtt instances, saving 2 pages + structs per ppgtt.
v2: Rebase
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
On 29/05/15 07:26, Jani Nikula wrote:
On Fri, 29 May 2015, Shuah Khan shua...@osg.samsung.com wrote:
I am seeing the following in the dmesg on 4.0.4 with rt patch
[5.720319] [ cut here ]
[5.720347] WARNING: CPU: 6 PID: 466 at
On 5/22/2015 6:05 PM, Mika Kuoppala wrote:
There is no need for atomicity here. Convert all bitmap
operations to nonatomic variants.
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
Reviewed-by: Michel Thierry michel.thie...@intel.com
---
Hey,
Op 04-06-15 om 01:33 schreef Matt Roper:
On Wed, Jun 03, 2015 at 12:32:43PM -0700, Konduru, Chandra wrote:
-Original Message-
From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
Sent: Wednesday, June 03, 2015 12:02 AM
To: Konduru, Chandra; Roper, Matthew D
Cc:
On Thu, 2015-05-21 at 23:29 +0200, Daniel Vetter wrote:
On Thu, May 21, 2015 at 10:35:07PM +0530, Animesh Manna wrote:
On 5/21/2015 5:41 PM, Daniel Vetter wrote:
On Thu, May 21, 2015 at 03:49:52PM +0530, Animesh Manna wrote:
Before enabling dc5/dc6, used wait for completion instead of
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