2015-08-17 17:06 GMT-03:00 Paulo Zanoni przan...@gmail.com:
2015-08-12 12:44 GMT-03:00 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Eliminate a bunch of duplicated code that calculates the currently
enabled HPD interrupt bits.
Nice one! I see this one
On 2015-08-26 10:33, Daniel Vetter wrote:
On Wed, Aug 19, 2015 at 10:48:55AM +0200, David Henningsson wrote:
This callback will be called by the i915 driver to notify the hda
driver that its HDMI information needs to be refreshed, i e,
that audio output is now available (or unavailable) -
2015-08-12 12:44 GMT-03:00 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Make LPT:LP checks look neater by wrapping the details in a
new HAS_PCH_LPT_LP() macro.
This has the potential to be confusing since HAS_PCH_LPT() is also
true for cases where
Very strictly speaking this is possible if you have special hw and
genlocked CRTCs. In general switching a plane between two active CRTC
just won't work so well and is probably not tested at all. Just forbid
it.
I've put this into the core since right now no helper or driver copes
with it, no
2015-08-12 12:44 GMT-03:00 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
The PORTA HPD defines are not BXT specific. They also exist on SPT,
and partially already on LPT:LP.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
On Wed, Aug 26, 2015 at 11:41 AM, Daniel Vetter daniel.vet...@ffwll.ch wrote:
Very strictly speaking this is possible if you have special hw and
genlocked CRTCs. In general switching a plane between two active CRTC
just won't work so well and is probably not tested at all. Just forbid
it.
So,
On Wed, Aug 26, 2015 at 12:07:30PM -0400, Rob Clark wrote:
On Wed, Aug 26, 2015 at 12:03 PM, Rob Clark robdcl...@gmail.com wrote:
On Wed, Aug 26, 2015 at 11:41 AM, Daniel Vetter daniel.vet...@ffwll.ch
wrote:
Very strictly speaking this is possible if you have special hw and
genlocked
On Wed, Aug 26, 2015 at 01:38:36PM -0400, Rob Clark wrote:
On Wed, Aug 26, 2015 at 12:30 PM, Ville Syrjälä
ville.syrj...@linux.intel.com wrote:
On Wed, Aug 26, 2015 at 12:07:30PM -0400, Rob Clark wrote:
On Wed, Aug 26, 2015 at 12:03 PM, Rob Clark robdcl...@gmail.com wrote:
On Wed, Aug 26,
On Wed, Aug 26, 2015 at 04:13:52PM -0300, Paulo Zanoni wrote:
2015-08-12 12:44 GMT-03:00 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
The PORTA HPD defines are not BXT specific. They also exist on SPT,
and partially already on LPT:LP.
2015-08-17 16:51 GMT-03:00 Paulo Zanoni przan...@gmail.com:
2015-08-12 12:44 GMT-03:00 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Indent the PORTx_HOTPLUG_... defines appropriately, and fix some space
vs. tab issues.
Signed-off-by: Ville Syrjälä
On Wed, 26 Aug 2015, Jindal, Sonika sonika.jin...@intel.com wrote:
Oh, bxt is here..:) Spoke too soon..
But will need to make it based upon intel_encoder-hpd_pin because of the
A0/A1 WA for BXT.
That should anyway be a separate patch changing the port-port to a port
acquired from pin_to_port.
On Mon, Aug 17, 2015 at 05:19:09PM +, Zanoni, Paulo R wrote:
Em Sex, 2015-08-14 às 12:35 +0200, Thierry Reding escreveu:
From: Thierry Reding tred...@nvidia.com
The gtt.stolen_size field is of type size_t, and so should be printed
using %zu to avoid build warnings on either 32-bit
On Fri, Aug 14, 2015 at 05:18:27PM +0100, Chris Wilson wrote:
On Fri, Aug 14, 2015 at 06:43:30PM +0300, Imre Deak wrote:
Due to a coherency issue on BXT A steppings we can't guarantee a
coherent view of cached (CPU snooped) GPU mappings, so fail such
requests. User space is supposed to fall
The cleanup series has already been reviewed, this one hasn't. The
cleanup series should actually make patch 3/4 simpler to
review. Otherwise there really isn't conflict.
BR,
Jani.
On Wed, 26 Aug 2015, Hindman, Gavin gavin.hind...@intel.com wrote:
Jani - do you believe that this series will
On Wed, Aug 19, 2015 at 04:46:13PM +0300, Mika Kuoppala wrote:
Arun Siluvery arun.siluv...@linux.intel.com writes:
MI_STORE_REGISTER_MEM, MI_LOAD_REGISTER_MEM instructions are not really
variable length instructions unlike MI_LOAD_REGISTER_IMM where it expects
(reg, addr) pairs so use
That seems to be a typo. The original code will override the previous
list empty check value in the loop. As the result, only the last vm in
vm_list impacts the empty check. The problem is fixed by using local
bool variable inside the loop.
Signed-off-by: Zhiyuan Lv zhiyuan...@intel.com
---
On Mon, Aug 24, 2015 at 04:38:23PM -0700, Rodrigo Vivi wrote:
We also need to call the frontbuffer flip to trigger proper
invalidations when disabling planes. Otherwise we will miss
screen updates when disabling sprites or cursor.
On core platforms where HW tracking also works, this issue
Hi, Tiago.
On 08/26/2015 02:02 AM, Tiago Vignatti wrote:
From: Daniel Vetter daniel.vet...@ffwll.ch
The userspace might need some sort of cache coherency management e.g. when CPU
and GPU domains are being accessed through dma-buf at the same time. To
circumvent this problem there are
On Wed, Aug 26, 2015 at 06:27:36PM +0300, Mika Kuoppala wrote:
Chris Wilson ch...@chris-wilson.co.uk writes:
Delay the expensive read on the FPGA_DBG register from once per mmio to
once per forcewake section when we are doing the general wellbeing
check rather than the targetted error
On Tue, Aug 25, 2015 at 09:33:41PM -0700, Hindman, Gavin wrote:
Does this series comprehend all of the ddr-dvfs/PM-5 watermark reworks that
Ville did towards the end of CHV, or is this series additive to that?
Are you referring to the series
[PATCH 00/10] drm/i915: Another WM rewrite to
On Wed, 2015-08-26 at 11:15 +0300, Jani Nikula wrote:
On Thu, 13 Aug 2015, Jindal, Sonika sonika.jin...@intel.com
wrote:
On 8/13/2015 8:57 AM, Zhang, Xiong Y wrote:
On Wed, 2015-08-12 at 02:20 +, Zhang, Xiong Y wrote:
On Tue, 2015-08-11 at 07:05 +, Zhang, Xiong Y wrote:
On Wed, Aug 26, 2015 at 08:37:41AM -0700, Matt Roper wrote:
On Wed, Aug 26, 2015 at 04:39:12PM +0300, Ville Syrjälä wrote:
On Thu, Aug 20, 2015 at 06:11:53PM -0700, Matt Roper wrote:
Just pull the info out of the CRTC state structure rather than staging
it in an additional structure.
On Wed, Aug 26, 2015 at 12:03 PM, Rob Clark robdcl...@gmail.com wrote:
On Wed, Aug 26, 2015 at 11:41 AM, Daniel Vetter daniel.vet...@ffwll.ch
wrote:
Very strictly speaking this is possible if you have special hw and
genlocked CRTCs. In general switching a plane between two active CRTC
just
On Wed, 2015-08-26 at 11:06 +0200, Daniel Vetter wrote:
On Thu, Aug 20, 2015 at 04:12:00PM -0700, Rodrigo Vivi wrote:
From: Rodrigo Vivi vivi...@rdvivi-budapest.jf.intel.com
Let's use a native read with retry as suggested per spec to
fix Sink CRC on SKL when PSR is enabled.
With PSR
On Wed, Aug 26, 2015 at 1:53 PM, Ville Syrjälä
ville.syrj...@linux.intel.com wrote:
On Wed, Aug 26, 2015 at 01:38:36PM -0400, Rob Clark wrote:
On Wed, Aug 26, 2015 at 12:30 PM, Ville Syrjälä
ville.syrj...@linux.intel.com wrote:
On Wed, Aug 26, 2015 at 12:07:30PM -0400, Rob Clark wrote:
On
Forgot to do that in
commit d328c9d78d64ca11e744fe227096990430a88477
Author: Daniel Vetter daniel.vet...@ffwll.ch
Date: Fri Apr 10 16:22:37 2015 +0200
drm/i915: Select starting pipe bpp irrespective or the primary plane
and it's confusing. Fix it.
Cc: Jesse Barnes
From: Ville Syrjälä ville.syrj...@linux.intel.com
Make the code mode readable by pulling the does this crtc have any
encoders? deduction into a separate function.
Cc: Maarten Lankhorst maarten.lankho...@linux.intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
From: Ville Syrjälä ville.syrj...@linux.intel.com
The BIOS sometimes likes to enable pipes w/o any ports, at least on
older machines. Currently we fail to assign anything sensible to
crtc-hwmode.crtc_clock which leads to complaints from the vblank code.
Deal with active pipes w/o ports and assign
Attach the some introduction to help the discussion:
[ Current Implementation - Performance Oriented ! ]
Guest create Guest submits
a new context its context
+
On Wed, Aug 26, 2015 at 12:30 PM, Ville Syrjälä
ville.syrj...@linux.intel.com wrote:
On Wed, Aug 26, 2015 at 12:07:30PM -0400, Rob Clark wrote:
On Wed, Aug 26, 2015 at 12:03 PM, Rob Clark robdcl...@gmail.com wrote:
On Wed, Aug 26, 2015 at 11:41 AM, Daniel Vetter daniel.vet...@ffwll.ch
On Wed, Aug 26, 2015 at 05:41:23PM +0200, Daniel Vetter wrote:
Very strictly speaking this is possible if you have special hw and
genlocked CRTCs. In general switching a plane between two active CRTC
just won't work so well and is probably not tested at all. Just forbid
it.
I've put this
On Wed, 2015-08-26 at 18:53 +0300, Ville Syrjälä wrote:
On Wed, Aug 26, 2015 at 05:41:23PM +0200, Daniel Vetter wrote:
Very strictly speaking this is possible if you have special hw and
genlocked CRTCs. In general switching a plane between two active
CRTC
just won't work so well and is
On 08/26/2015 12:58 AM, Jani Nikula wrote:
Normally we determine the backlight PWM modulation frequency (which we
also use as backlight max value) from the backlight registers at module
load time, expecting the registers have been initialized by the BIOS. If
this is not the case, we fail.
The
2015-08-12 12:44 GMT-03:00 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Starting from SPT the only interrupts living in the south are GMBUS and
HPD. What's worse some of the SPT specific new bits conflict with some
other bits on earlier PCH generations. So
On Wed, Aug 26, 2015 at 3:49 PM, Daniel Vetter daniel.vet...@ffwll.ch wrote:
Very strictly speaking this is possible if you have special hw and
genlocked CRTCs. In general switching a plane between two active CRTC
just won't work so well and is probably not tested at all. Just forbid
it.
From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
On Wed, Aug 26, 2015 at 04:13:52PM -0300, Paulo Zanoni wrote:
...
Although the doc for LPT _suggests_ this is only for LPT:LP, it
doesn't mark this bit as LPT:LP-specific just like it marks all the
other LPT:LP-specific bits in every
On 08/26/2015 12:58 AM, Jani Nikula wrote:
Make it available outside of intel_dp.c.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 33 +
drivers/gpu/drm/i915/intel_dp.c | 34 --
On 08/26/2015 12:58 AM, Jani Nikula wrote:
This is a rebase of [1] and originally [2]. I haven't tried this in a
year and I have no idea if it works on SKL, and it's not implemented for
BXT. However there's renewed interest, so here's the rebase.
Renewed interest as an ODM has been reporting
This partially reverts commit 74c090b1bdc57b1c9f1361908cca5a3d8a80fb08.
The DRIVER_ATOMIC cap cannot yet be exported because i915 lacks async
support.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.c| 2 +-
Normally we determine the backlight PWM modulation frequency (which we
also use as backlight max value) from the backlight registers at module
load time, expecting the registers have been initialized by the BIOS. If
this is not the case, we fail.
The VBT contains the backlight modulation
This is a rebase of [1] and originally [2]. I haven't tried this in a
year and I have no idea if it works on SKL, and it's not implemented for
BXT. However there's renewed interest, so here's the rebase.
BR,
Jani.
[1] http://mid.gmane.org/cover.1431003197.git.jani.nik...@intel.com
[2]
Delay the expensive read on the FPGA_DBG register from once per mmio to
once per forcewake section when we are doing the general wellbeing
check rather than the targetted error detection. This almost reduces
the overhead of the debug facility (for example when submitting execlists)
to zero whilst
Make it available outside of intel_dp.c.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 33 +
drivers/gpu/drm/i915/intel_dp.c | 34 --
drivers/gpu/drm/i915/intel_drv.h | 1 +
3
On Thu, 13 Aug 2015, Jindal, Sonika sonika.jin...@intel.com wrote:
On 8/13/2015 8:57 AM, Zhang, Xiong Y wrote:
On Wed, 2015-08-12 at 02:20 +, Zhang, Xiong Y wrote:
On Tue, 2015-08-11 at 07:05 +, Zhang, Xiong Y wrote:
-Original Message-
From: Vivi, Rodrigo
Sent: Saturday,
On Wed, Aug 19, 2015 at 10:48:55AM +0200, David Henningsson wrote:
This callback will be called by the i915 driver to notify the hda
driver that its HDMI information needs to be refreshed, i e,
that audio output is now available (or unavailable) - usually as a
result of a monitor being plugged
On Wed, Aug 19, 2015 at 06:02:35PM -0700, Chandra Konduru wrote:
Adding driver workarounds for nv12.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 20
drivers/gpu/drm/i915/intel_csr.c |2 +-
On Thu, Aug 20, 2015 at 05:55:41PM -0700, Rodrigo Vivi wrote:
At the beginning it was masked to allow PSR at all.
Than it got removed later by my
commit 09108b90f040 (drm/i915: PSR: Remove Low Power HW tracking mask.)
in order to trying fixing one case reported at intel-gfx mailing list
where
On Tue, 25 Aug 2015, Sivakumar Thulasimani sivakumar.thulasim...@intel.com
wrote:
From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com
This patch checks for changes in sink count between short pulse
hpds and forces full detect when there is a change. This will
result in compliance
On Wed, Aug 26, 2015 at 03:01:26PM +0800, Zhiyuan Lv wrote:
That seems to be a typo. The original code will override the previous
list empty check value in the loop. As the result, only the last vm in
vm_list impacts the empty check. The problem is fixed by using local
bool variable inside the
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 7223
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK -2
On 08/25/2015 10:18 PM, Chris Wilson wrote:
A long time ago (before 3.14) we relied on a permanent pinning of the
ifbdev to lock the fb in place inside the GGTT. However, the
introduction of stealing the BIOS framebuffer and reusing its address in
the GGTT for the fbdev has muddied waters and
On Wed, Aug 19, 2015 at 06:05:25PM -0700, Chandra Konduru wrote:
From: chandra konduru chandra.kond...@intel.com
This patch adds kms_nv12 test case. It covers testing NV12
in linear/tile-X/tile-Y tiling formats in 0/90/180/270
orientations. For each tiling format, it tests several
On 08/26/2015 10:42 AM, Archit Taneja wrote:
On 08/25/2015 07:15 PM, Daniel Vetter wrote:
Faster than recompiling.
Note that restore_fbdev_mode_unlocked is a bit special and the only
one which returns an error code when fbdev isn't there - i915 needs
that one to not fall over with some
On Wed, Aug 26, 2015 at 10:32:01AM +0200, Daniel Vetter wrote:
On Tue, Aug 18, 2015 at 04:06:17PM +0100, Chris Wilson wrote:
On Tue, Aug 18, 2015 at 03:55:07PM +0100, Nick Hoath wrote:
This is the wrong location. Just kill set_seqno, the experiment has run
its course and we now have a n
On Thu, Aug 20, 2015 at 10:47:35AM +0300, Jani Nikula wrote:
v2 with missing cases handled and intel_digital_port_connected return
value changed to bool. Mostly it's just the addition of patches 2 and 3,
and rebase of the rest.
Pulled in entire series, thanks.
-Daniel
BR,
Jani.
Jani
On Fri, Aug 21, 2015 at 09:40:12AM +0300, Jani Nikula wrote:
On Thu, 20 Aug 2015, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
We are no longer checkling the DP link status on long hpd. We used to do
that from the .hot_plug() handler, but it was
On Tue, 25 Aug 2015, Rodrigo Vivi rodrigo.v...@intel.com wrote:
SKL-Y can now use the same programming for all VccIO values after an
adjustment to I_boost.
SKL-U DP table adjustments.
1. Remove SKL Y 0.95V from SKL H and S columns in all tables. The
other SKL Y column removes the
On Fri, Aug 14, 2015 at 06:24:32PM +0100, Chris Wilson wrote:
The PIPE.STAT register contains some interrupt status bits per pipe, and
if assert cause the corresponding bit in the IIR to be asserted (thus
raising an interrupt). When handling an interrupt, we should clear the
PIPE.STAT
On Wed, Aug 19, 2015 at 02:55:34PM +0300, Ville Syrjälä wrote:
On Sat, Aug 15, 2015 at 09:30:18AM +0100, Chris Wilson wrote:
On Fri, Aug 14, 2015 at 06:34:18PM -0300, Paulo Zanoni wrote:
The spec says we just can't use it.
But what about when we inherit a framebuffer at that address?
Op 26-08-15 om 09:51 schreef Daniel Vetter:
On Mon, Aug 17, 2015 at 12:00:38PM +0200, Maarten Lankhorst wrote:
Set DRIVER_MODESET and DRIVER_ATOMIC by default. The driver is fully atomic.
Remove the legacy suspend/resume, to fix a warning introduced by:
drm: WARN_ON if a modeset driver uses
On Tue, Aug 18, 2015 at 01:56:08PM +0200, Maarten Lankhorst wrote:
Hey,
Op 17-08-15 om 17:05 schreef ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
With MST there won't be a crtc assigned to the main link encoder, so
trying to dig up the pipe_config
On Wed, Aug 26, 2015 at 09:57:45AM +0200, Maarten Lankhorst wrote:
Op 26-08-15 om 09:51 schreef Daniel Vetter:
On Mon, Aug 17, 2015 at 12:00:38PM +0200, Maarten Lankhorst wrote:
.load = i915_driver_load,
.unload = i915_driver_unload,
.open = i915_driver_open,
@@ -1655,10
Hi Daniel,
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of
Daniel Vetter
Sent: Wednesday, August 26, 2015 4:18 PM
To: Yang, Libin
Cc: alsa-de...@alsa-project.org; ti...@suse.de; intel-
g...@lists.freedesktop.org; daniel.vet...@ffwll.ch;
On Fri, Aug 21, 2015 at 02:52:54PM +0300, Mika Kahola wrote:
On Fri, 2015-08-21 at 13:58 +0300, Ville Syrjälä wrote:
On Tue, Aug 18, 2015 at 02:37:02PM +0300, Mika Kahola wrote:
It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
On Mon, Aug 24, 2015 at 03:36:46PM +0300, Joonas Lahtinen wrote:
On pe, 2015-08-21 at 10:24 +0800, Zhiyuan Lv wrote:
Hi Joonas,
Thanks for the review! And my reply inline.
Regards,
-Zhiyuan
On Thu, Aug 20, 2015 at 02:23:11PM +0300, Joonas Lahtinen wrote:
Hi,
On to,
On Tue, 25 Aug 2015, Sivakumar Thulasimani sivakumar.thulasim...@intel.com
wrote:
From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com
This patch reads sink_count dpcd always and removes its
read operation based on values in downstream port dpcd. Also
we should read it irrespective of
On 8/26/2015 3:17 PM, Jani Nikula wrote:
On Tue, 25 Aug 2015, Sivakumar Thulasimani sivakumar.thulasim...@intel.com
wrote:
From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com
This patch reads sink_count dpcd always and removes its
read operation based on values in downstream port
On Tue, Aug 25, 2015 at 07:03:42PM -0300, Paulo Zanoni wrote:
The unclaimed register bit is only triggered when someone touches the
specified register range.
For the normal use case (with i915.mmio_debug=0), this commit will
avoid the extra __raw_i915_read32() call for every register outside
On Mon, Aug 17, 2015 at 12:00:38PM +0200, Maarten Lankhorst wrote:
Set DRIVER_MODESET and DRIVER_ATOMIC by default. The driver is fully atomic.
Remove the legacy suspend/resume, to fix a warning introduced by:
drm: WARN_ON if a modeset driver uses legacy suspend/resume helpers
and removing
On Tue, Aug 18, 2015 at 02:51:51PM +0800, libin.y...@intel.com wrote:
From: Libin Yang libin.y...@intel.com
Add the sync_audio_rate callback.
With the callback, audio driver can trigger
i915 driver to set the proper N/CTS or N/M
based on different sample rates.
Signed-off-by: Libin
On Wed, 26 Aug 2015, Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Aug 17, 2015 at 03:20:38PM +0300, Jani Nikula wrote:
On Mon, 17 Aug 2015, libin.y...@intel.com wrote:
From: Libin Yang libin.y...@intel.com
HDMI audio may not work at some frequencies
with the HW provided N/CTS.
This
On Mon, 2015-08-24 at 14:40 +0100, Thomas Wood wrote:
On 20 August 2015 at 15:43, Ander Conselvan de Oliveira
ander.conselvan.de.olive...@intel.com wrote:
The drm core doesn't check unused fields of ADDFB2 for pre-FB_MODIFIERS
userspace, so require that and use the local version of the
On Tue, Aug 18, 2015 at 04:06:17PM +0100, Chris Wilson wrote:
On Tue, Aug 18, 2015 at 03:55:07PM +0100, Nick Hoath wrote:
This is the wrong location. Just kill set_seqno, the experiment has run
its course and we now have a n igt to exercise seqno wraparound.
It has to be here as the seqno
On Tue, Aug 25, 2015 at 05:10:54PM +0100, Graham Whaley wrote:
On Tue, 2015-08-25 at 16:29 +0200, Daniel Vetter wrote:
On Tue, Aug 25, 2015 at 10:26:44AM +0100, Graham Whaley wrote:
The KMS Properties table is in HTML format, which is not supported
for building pdfdocs, resulting in the
HPD bits control the interrupt but the live status (with some monitors) takes
time to get set.
We had experienced this with VLV and CHV with few monitors.
So Android code always has this retry for live status.
Yes, this was not added in the previous series because we planned to add the
next set
On 08/17/2015 05:23 PM, Ville Syrjälä wrote:
On Mon, Aug 17, 2015 at 09:46:01AM +0530, Deepak wrote:
On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Move the CHV clock buffer disable from chv_disable_pll() to the new
encoder
On Wed, Jul 08, 2015 at 11:45:54PM +0300, ville.syrj...@linux.intel.com wrote:
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index dab1da9..506a8cc 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++
The drm core doesn't check unused fields of ADDFB2 for pre-FB_MODIFIERS
userspace, so use igt_require_fb_modifiers(). Also, the size of the
ioctl changed with the addition of the modifiers, so it is necessary to
use the LOCAL_ version of it, otherwise some data may get truncated.
v2: Improve
This fixes kms_universal_plane.universal-plane-pipe-A-functional.
IPS gets enabled even though the primary plane is disabled. This is
not supported, and results in warnings like below:
[ cut here ]
WARNING: CPU: 0 PID: 1707 at drivers/gpu/drm/i915/intel_display.c:1354
On Tue, Aug 25, 2015 at 08:17:05AM +0800, Zhiyuan Lv wrote:
Hi Chris,
On Mon, Aug 24, 2015 at 11:23:13AM +0100, Chris Wilson wrote:
On Mon, Aug 24, 2015 at 06:04:28PM +0800, Zhiyuan Lv wrote:
Hi Chris,
On Thu, Aug 20, 2015 at 09:36:00AM +0100, Chris Wilson wrote:
On Thu, Aug
This is done through pre_disable_primary and hsw_disable_ips.
They're both set on the same conditions, so leave the check of
disable_ips in pre_disable_primary.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 16 +---
On Tue, Aug 25, 2015 at 05:31:33PM +0530, Sonika Jindal wrote:
Some monitors take time in setting the live status.
So retry for few times if this is a connect HPD
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
Why was this bugfix not part of the original series? Now I have to retest
on
On Wed, Aug 26, 2015 at 10:26:35AM +0300, Jani Nikula wrote:
On Wed, 26 Aug 2015, Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Aug 17, 2015 at 05:19:09PM +, Zanoni, Paulo R wrote:
Em Sex, 2015-08-14 às 12:35 +0200, Thierry Reding escreveu:
From: Thierry Reding tred...@nvidia.com
On Mon, Aug 17, 2015 at 01:45:01PM -0300, Paulo Zanoni wrote:
2015-08-17 13:30 GMT-03:00 Dave Gordon david.s.gor...@intel.com:
The current versions of these two macros don't work correctly if the
argument expression happens to contain a modulo operator (%) -- when
stringified, it gets
Hi Chris,
Thanks for the reply! Do you mean we could completely delete
i915_gem_evict_everything() and rely on others to do gem_retire_requests()?
Sorry that I am still learning the code :-)
Regards,
-Zhiyuan
On Wed, Aug 26, 2015 at 08:28:43AM +0100, Chris Wilson wrote:
On Wed, Aug 26, 2015 at
Hi Daniel,
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of
Daniel Vetter
Sent: Wednesday, August 26, 2015 3:53 PM
To: Jani Nikula
Cc: Yang, Libin; alsa-de...@alsa-project.org; ti...@suse.de; intel-
g...@lists.freedesktop.org;
We can forgo an evict-everything here as the shrinker operation itself
will unbind any vma as required. If we explicitly idle the GPU through a
switch to the default context, we not only create a request in an
illegal context (e.g. whilst shrinking during execbuf with a request
already allocated),
With UMS gone, we no longer use it during suspend. And with the last
user removed from the shrinker, we can remove the dead code.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_gem_evict.c | 45
Exclude active GPU pages from the purview of the background shrinker
(kswapd), as these cause uncontrollable GPU stalls. Given that the
shrinker is rerun until the freelists are satisfied, we should have
opportunity in subsequent passes to recover the pages once idle. If the
machine does run out
On Wed, Aug 26, 2015 at 08:29:09AM +, Yang, Libin wrote:
Hi Daniel,
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of
Daniel Vetter
Sent: Wednesday, August 26, 2015 4:18 PM
To: Yang, Libin
Cc: alsa-de...@alsa-project.org; ti...@suse.de;
On Fri, Aug 21, 2015 at 04:08:41PM +0100, Chris Wilson wrote:
In order to flush the results from in-batch pipecontrol writes (used for
example in glQuery) before declaring the batch complete (and so declaring
the query results coherent), we need to set the FlushEnable bit in our
flushing
On Mon, Aug 24, 2015 at 05:28:13PM +0530, ankitprasad.r.sha...@intel.com wrote:
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
We are trying to reduce the time for which the global 'struct_mutex'
is locked. Execbuffer ioctl is one place where it is generally held
for the longest
On Sun, Aug 23, 2015 at 05:52:47PM +0530, Sagar Arun Kamble wrote:
On BXT, We Observe timeout for forcewake request completion with 2ms polling
period as given here:
[drm:fw_domains_get] ERROR render: timed out waiting for forcewake ack
request.
Polling for 50ms is recommended to avoid
On 8/26/2015 3:32 PM, Jani Nikula wrote:
On Tue, 25 Aug 2015, Sivakumar Thulasimani sivakumar.thulasim...@intel.com
wrote:
From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com
This patch checks for changes in sink count between short pulse
hpds and forces full detect when there is a
From: Daniel Vetter daniel.vet...@intel.com
If we really want to we can be more verbose here, but we really don't
need an entire function for this.
Cc: Damien Lespiau damien.lesp...@intel.com
Cc: Imre Deak imre.d...@intel.com
Cc: Sunil Kamath sunil.kam...@intel.com
Signed-off-by: Daniel Vetter
From: Daniel Vetter daniel.vet...@intel.com
We need to make sure we don't put garbage into the hw if dmc firmware
loading failed mid-thru.
Cc: Damien Lespiau damien.lesp...@intel.com
Cc: Imre Deak imre.d...@intel.com
Cc: Sunil Kamath sunil.kam...@intel.com
Signed-off-by: Daniel Vetter
From: Daniel Vetter daniel.vet...@intel.com
As all csr firmware related opertion are not using any
any data structures of drm framework level, so better to
use dev_priv instead of dev. it's a new style! :)
Cc: Damien Lespiau damien.lesp...@intel.com
Cc: Imre Deak imre.d...@intel.com
Cc: Sunil
From: Daniel Vetter daniel.vet...@intel.com
The loader function will get a bit more complicated soon, extract the
parsing code to make the control flow clearer. While doing that just
use dev_priv-csr.dmc_payload as the indicator for whether it all
suceeded or not.
Cc: Damien Lespiau
From: Daniel Vetter daniel.vet...@intel.com
Two benefits:
- We can use FW_LOADER_USERSPACE_FALLBACK.
- We can use flush_work to synchronize with the oustanding worker,
which is a notch more obvious what it does than having a special
completion.
The next patch will properly synchronize
Condition check for out of boundary for csr address space is corrected
(Thanks to David Binderman for suggestion).
Cc: Imre Deak imre.d...@intel.com
Signed-off-by: Animesh Manna animesh.ma...@intel.com
---
drivers/gpu/drm/i915/intel_csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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