[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: implement WaClearTdlStateAckDirtyBits

== Series Details == Series: drm/i915: implement WaClearTdlStateAckDirtyBits URL : https://patchwork.freedesktop.org/series/4282/ State : failure == Summary == CC [M] drivers/net/ethernet/intel/igbvf/ethtool.o LD drivers/usb/storage/built-in.o CC [M]

Re: [Intel-gfx] [PATCH] drm/i915: implement WaClearTdlStateAckDirtyBits

On 09/03/2016 16:46, tim.g...@intel.com wrote: From: Tim Gore This is to fix a GPU hang seen with mid thread pre-emption and pooled EUs. Signed-off-by: Tim Gore --- drivers/gpu/drm/i915/i915_reg.h | 12 drivers/gpu/drm/i915/intel_lrc.c

Re: [Intel-gfx] [PATCH] drm/i915: add sanity check for partial view creation

> If this concerns you that, please look at the API, and please review the outstanding patches. Could you elaborate on this please? What patches are you referring to? ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org

Re: [Intel-gfx] [PATCH v4] drm/i915: Support to enable TRTT on GEN9

On 3/9/2016 9:51 PM, Chris Wilson wrote: On Wed, Mar 09, 2016 at 09:26:08PM +0530, Goel, Akash wrote: On 3/9/2016 8:32 PM, Chris Wilson wrote: On Wed, Mar 09, 2016 at 08:20:07PM +0530, Goel, Akash wrote: What locks are we holding here? + else if (args->size < sizeof(trtt_params))

[Intel-gfx] [PATCH] drm/i915: implement WaClearTdlStateAckDirtyBits

From: Tim Gore This is to fix a GPU hang seen with mid thread pre-emption and pooled EUs. Signed-off-by: Tim Gore --- drivers/gpu/drm/i915/i915_reg.h | 12 drivers/gpu/drm/i915/intel_lrc.c | 19 +++ 2 files changed, 31

[Intel-gfx] [PATCH 5/5] drm/i915: s/crtc_state/old_crtc_state/ in intel_atomic_commit()

From: Ville Syrjälä Avoid some head spinning by renaming the crtc_state variable to old_crtc_state. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 20 ++-- 1 file changed, 10 insertions(+),

Re: [Intel-gfx] [PATCH 4/7] drm/i915: Move load time display/audio callback init earlier

Hi Imre, [auto build test WARNING on drm-intel/for-linux-next] [also build test WARNING on next-20160309] [cannot apply to v4.5-rc7] [if your patch is applied to the wrong git tree, please drop us a note to help improving the system] url: https://github.com/0day-ci/linux/commits/Imre-Deak

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: CHV regressions fixes

On Wed, Mar 09, 2016 at 05:31:34PM -, Patchwork wrote: > == Series Details == > > Series: drm/i915: CHV regressions fixes > URL : https://patchwork.freedesktop.org/series/4283/ > State : failure > > == Summary == > > Series 4283v1 drm/i915: CHV regressions fixes >

[Intel-gfx] [PATCH 0/5] drm/i915: CHV regressions fixes

From: Ville Syrjälä CHV display side got broken on multiple fronts. This series undoes the damage a bit and I tossed in a few cleanupish things at the end for fun. Ville Syrjälä (5): Revert "drm/i915: Enable PSR by default on Valleyview and Cherryview."

[Intel-gfx] [PATCH 4/5] drm/i915: Wait for vblank after cxsr disable in pre_plane_update

From: Ville Syrjälä We must wait for the hardware to exit cxsr before doing the plane update, so add the missing vblank wait to pre_plane_update after disabling cxsr. We have the wait for vblank in the pre_disable_primary hook, but not in the pre_plane_update

[Intel-gfx] [PATCH 1/5] Revert "drm/i915: Enable PSR by default on Valleyview and Cherryview."

From: Ville Syrjälä This reverts commit a38c274faad0ec6aba692e294ec751d04dbba803. PSR causes all sorts of vblank wait timeouts and whanot on CHV. Disable it again. Cc: Rodrigo Vivi Fixes: a38c274faad0 ("drm/i915: Enable PSR by default on

[Intel-gfx] [PATCH 3/5] drm/i915: Fix watermarks for VLV/CHV

From: Ville Syrjälä commit 92826fcdfc14 ("drm/i915: Calculate watermark related members in the crtc_state, v4.") broke thigns by removing the pre vs. post wm update distinction. We also lost the pre plane wm update entirely for VLV/CHV from the crtc enable path.

[Intel-gfx] [PATCH 2/5] drm/i915: Pass the correct crtc state to .update_plane()

From: Ville Syrjälä Pass the current crtc state, not the old crtc state, to the .update_plane() hook. Noticed on BSW when PRIMSIZE was getting programmed to a stale value which produced utter garbage on screen eg. wwhen going from 1920x1080 to 1024x768. Cc:

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: CHV regressions fixes

== Series Details == Series: drm/i915: CHV regressions fixes URL : https://patchwork.freedesktop.org/series/4283/ State : failure == Summary == Series 4283v1 drm/i915: CHV regressions fixes http://patchwork.freedesktop.org/api/1.0/series/4283/revisions/1/mbox/ Test drv_module_reload_basic:

Re: [Intel-gfx] [PATCH] drm/i915: implement WaClearTdlStateAckDirtyBits

Hi Tim, [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on v4.5-rc7 next-20160309] [if your patch is applied to the wrong git tree, please drop us a note to help improving the system] url: https://github.com/0day-ci/linux/commits/tim-gore-intel-com/drm-i915

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915/gen9: add WaClearFlowControlGpgpuContextSave (rev2)

== Series Details == Series: drm/i915/gen9: add WaClearFlowControlGpgpuContextSave (rev2) URL : https://patchwork.freedesktop.org/series/4272/ State : warning == Summary == Series 4272v2 drm/i915/gen9: add WaClearFlowControlGpgpuContextSave

Re: [Intel-gfx] [PATCH] drm/i915: implement WaClearTdlStateAckDirtyBits

Hi Tim, [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on v4.5-rc7 next-20160309] [if your patch is applied to the wrong git tree, please drop us a note to help improving the system] url: https://github.com/0day-ci/linux/commits/tim-gore-intel-com/drm-i915

Re: [Intel-gfx] [PATCH] drm/i915: implement WaClearTdlStateAckDirtyBits

On 09/03/2016 16:46, tim.g...@intel.com wrote: From: Tim Gore This is to fix a GPU hang seen with mid thread pre-emption and pooled EUs. Signed-off-by: Tim Gore --- drivers/gpu/drm/i915/i915_reg.h | 12 drivers/gpu/drm/i915/intel_lrc.c

Re: [Intel-gfx] [PATCH 1/5] Revert "drm/i915: Enable PSR by default on Valleyview and Cherryview."

Acked-by: Rodrigo Vivi I confirm this is hitting BAT hard on CHV. I'm working here to handle this PSR exit on VBlanks on CHV already, but the vblanks spinlocks are giving me headaches... So better to revert. thanks for the finding, ideas and this revert... On Wed,

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Support to enable TRTT on GEN9 (rev5)

== Series Details == Series: drm/i915: Support to enable TRTT on GEN9 (rev5) URL : https://patchwork.freedesktop.org/series/2321/ State : failure == Summary == CC drivers/usb/storage/usual-tables.o CC [M] drivers/net/ethernet/intel/igb/e1000_mbx.o CC [M]

Re: [Intel-gfx] [iGVT-g] Ask for comments of getting guest framebuffer in igvt-g

> From: Gerd Hoffmann [mailto:kra...@redhat.com] > Sent: Tuesday, March 08, 2016 4:37 PM > > Hi, > > > btw I don't think this vblank issue would be very significant. The main > > targeted usage of GVT-g is for server virtualization/cloud, where > > a remoting protocol is required for customer

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915/skl: SKL CDCLK change on modeset tracking VCO (rev7)

== Series Details == Series: drm/i915/skl: SKL CDCLK change on modeset tracking VCO (rev7) URL : https://patchwork.freedesktop.org/series/1609/ State : warning == Summary == Series 1609v7 drm/i915/skl: SKL CDCLK change on modeset tracking VCO

[Intel-gfx] [PATCH v5] drm/i915: Support to enable TRTT on GEN9

From: Akash Goel Gen9 has an additional address translation hardware support in form of Tiled Resource Translation Table (TR-TT) which provides an extra level of abstraction over PPGTT. This is useful for mapping Sparse/Tiled texture resources. Sparse resources are created

[Intel-gfx] [PATCH V8] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

From: Clint Taylor WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected to DDI1 the system will hard hang during a cold boot. Occurs when DDI1 is enabled when the cdclk is less then required. DP connected to DDI2 and HPD on either port works

Re: [Intel-gfx] [PATCH v5 00/12] Enable GPU switching on pre-retina?MacBook Pro

> > To sum up, and if we take the above patches into consideration: > - on boot, one or more GPUs are powered on, an init script would queue > a GPU switch to the integrated one. The other GPU would be switched off > (automatically?) > - when X/wayland is running, queue the requests using DIGD or

[Intel-gfx] [PATCH] drm/i915/gen9: add WaClearFlowControlGpgpuContextSave

From: Tim Gore This allows writes to EU flow control registers. Together with SIP code from the user-mode driver this resolves a hang seen in some pre-emption scenarios. Note that this patch is just the kernel mode part of this workaround. Signed-off-by: Tim Gore

[Intel-gfx] [PATCH v2] drm/i915: Fix races on fbdev

The ->lastclose callback invokes intel_fbdev_restore_mode() and has been witnessed to run before intel_fbdev_initial_config_async() has finished. We might likewise receive hotplug events before we've had a chance to fully set up the fbdev. Fix by waiting for the asynchronous thread to finish.

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Fix races on fbdev (rev2)

== Series Details == Series: drm/i915: Fix races on fbdev (rev2) URL : https://patchwork.freedesktop.org/series/4068/ State : failure == Summary == Series 4068v2 drm/i915: Fix races on fbdev http://patchwork.freedesktop.org/api/1.0/series/4068/revisions/2/mbox/ Test gem_ringfill:

[Intel-gfx] [PATCH 1/2] drm/i915: make device info bitfield flags bools

This is more robust for assignments and comparisons. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index

[Intel-gfx] [PATCH 2/2] drm/i915: don't mix bitwise and logical operations for has_snoop

Also make the code more readable. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_dma.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 4aa3db61a535..809d3783b033

Re: [Intel-gfx] [maintainer-tools PATCH] drm-intel: Add note about patches that move code between files

On 09/03/16 11:46, Ander Conselvan de Oliveira wrote: Patches that move big chunks of code between files can cause some complicated conflicts. Add a note to coordinate with maintainers before merging such patches. Signed-off-by: Ander Conselvan de Oliveira

[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915: make device info bitfield flags bools

== Series Details == Series: series starting with [1/2] drm/i915: make device info bitfield flags bools URL : https://patchwork.freedesktop.org/series/4270/ State : warning == Summary == Series 4270v1 Series without cover letter

[Intel-gfx] [PATCH i-g-t] drm_read: Remove use of DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID

Instead of checking that there's a CRTC in pipe 0 with a valid mode, check that we can get a vblank in the primary display controller. This should be equivalent, but also works with drivers other than i915. Signed-off-by: Tomeu Vizoso --- tests/drm_read.c | 39

Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915: Remove some post-commit members from intel_crtc->atomic, v3.

Op 09-03-16 om 10:59 schreef Patchwork: > == Series Details == > > Series: series starting with [1/2] drm/i915: Remove some post-commit members > from intel_crtc->atomic, v3. > URL : https://patchwork.freedesktop.org/series/4261/ > State : warning > > == Summary == > > Series 4261v1 Series

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Support to enable TRTT on GEN9 (rev4)

== Series Details == Series: drm/i915: Support to enable TRTT on GEN9 (rev4) URL : https://patchwork.freedesktop.org/series/2321/ State : failure == Summary == CC drivers/usb/host/xhci-hub.o CC [M] drivers/net/phy/bcm-phy-lib.o LD drivers/tty/serial/8250/8250_base.o CC [M]

[Intel-gfx] [maintainer-tools PATCH] drm-intel: Add note about patches that move code between files

Patches that move big chunks of code between files can cause some complicated conflicts. Add a note to coordinate with maintainers before merging such patches. Signed-off-by: Ander Conselvan de Oliveira --- drm-intel.rst | 4 1 file changed, 4

[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915: Remove some post-commit members from intel_crtc->atomic, v3.

== Series Details == Series: series starting with [1/2] drm/i915: Remove some post-commit members from intel_crtc->atomic, v3. URL : https://patchwork.freedesktop.org/series/4261/ State : warning == Summary == Series 4261v1 Series without cover letter

[Intel-gfx] [PATCH v4] drm/i915: Support to enable TRTT on GEN9

From: Akash Goel Gen9 has an additional address translation hardware support in form of Tiled Resource Translation Table (TR-TT) which provides an extra level of abstraction over PPGTT. This is useful for mapping Sparse/Tiled texture resources. Sparse resources are created

[Intel-gfx] [PATCH v4] igt/gem_trtt: Exercise the TRTT hardware

From: Akash Goel This patch provides the testcase to exercise the TRTT hardware. Some platforms have an additional address translation hardware support in form of Tiled Resource Translation Table (TR-TT) which provides an extra level of abstraction over PPGTT. This is

Re: [Intel-gfx] [PATCH v4] drm/i915: Support to enable TRTT on GEN9

On Wed, Mar 09, 2016 at 05:00:24PM +0530, akash.g...@intel.com wrote: > +static int > +intel_context_get_trtt(struct intel_context *ctx, > +struct drm_i915_gem_context_param *args) > +{ > + struct drm_i915_gem_context_trtt_param trtt_params; > + struct drm_device *dev =

[Intel-gfx] [PATCH 6/7] drm/i915: Move load time runtime device info init earlier

This init step accesses the device, but doesn't have any device specific side effect. It also sets up some platform specific attributes that may be required early, so move it earlier. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/i915_dma.c | 4 ++-- 1 file changed, 2

[Intel-gfx] [PATCH 3/7] drm/i915: Move load time IRQ SW init earlier

Most of the IRQ init is setting up callbacks so move that part earlier. Leave the pm_qos_add_request() call in place. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/i915_dma.c | 5 - drivers/gpu/drm/i915/i915_irq.c | 2 -- 2 files changed, 4 insertions(+), 3

[Intel-gfx] [PATCH 5/7] drm/i915: Move load time clock gating callback init earlier

Split out the part initing the clock gating callbacks and move it earlier. The rest of the callbacks in intel_init_pm() should be inited in the same way, but atm some of the callbacks are set only conditionally, so before doing this we need to make the setup unconditional and use instead some

[Intel-gfx] [PATCH 1/7] drm/i915: Add comments marking the start of load time init phases

To make it easier to get init time dependencies right during driver loading, define the following init phases: - state init not requiring device access - minimal HW setup to enable MMIO access to the device - state init requiring device access In the future the 3rd phase could be fine-grained

[Intel-gfx] [PATCH 4/7] drm/i915: Move load time display/audio callback init earlier

All of this is SW only initialization so we can move them earlier. Move the mutex init where the rest of the locks are inited. While at it also convert dev to dev_priv. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/i915_dma.c | 3 ++

[Intel-gfx] [PATCH 0/7] drm/i915: Move some load time init steps earlier

While working on the CDCLK init code I realized that the driver load time dependencies between the different init steps are rather difficult to follow and so it's not obvious where some new piece of initialization needs to be added. Also because some things are initialized too late, other steps

[Intel-gfx] [PATCH 7/7] drm/i915: Move load time runtime PM get later

We require the device to be powered only before accessing it, so we can move this call later. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/i915_dma.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_dma.c

Re: [Intel-gfx] [PATCH v4] drm/i915: Support to enable TRTT on GEN9

On 3/9/2016 8:32 PM, Chris Wilson wrote: On Wed, Mar 09, 2016 at 08:20:07PM +0530, Goel, Akash wrote: What locks are we holding here? + else if (args->size < sizeof(trtt_params)) + return -EINVAL; + else if (copy_from_user(_params, +

Re: [Intel-gfx] [PATCH 5/7] drm/i915: Move load time clock gating callback init earlier

On Wed, Mar 09, 2016 at 05:31:44PM +0200, Imre Deak wrote: > Split out the part initing the clock gating callbacks and move it > earlier. > > The rest of the callbacks in intel_init_pm() should be inited in the > same way, but atm some of the callbacks are set only conditionally, so > before

[Intel-gfx] [i-g-t PATCH v2 0/2] Avoid calling DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID

Hi, these two patches remove the two last uses of DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID, with the intention of making the tests runnable on !i915. I have looked in the kernel and cannot find any point where the pipe ID didn't match the index of the CRTC as returned by GETRESOURCES, so I'm not

[Intel-gfx] [i-g-t PATCH v2 1/2] lib: update kmstest_get_pipe_from_crtc_id

From: Micah Fedke This function uses an intel-specific ioctl to fetch a mapping between pipes and crtc ids, but this technique is outdated as the crtc id is now always equivalent to its index in the array of crtcs returned by the kernel. Signed-off-by: Tomeu Vizoso

[Intel-gfx] [i-g-t PATCH v2 2/2] overlay: Remove crtc<->pipe mapping code from kms-overlay

From: Micah Fedke the crtc id is now always equivalent to its index in the array of crtcs returned by the kernel Signed-off-by: Micah Fedke [tomeu: Fixed include path and removed some dead code] Signed-off-by: Tomeu Vizoso

[Intel-gfx] [PATCH] lib/igt_kms: Add COMMIT_ATOMIC to igt_display_commit2()

Co-Author : Marius Vlad Co-Author : Pratik Vishwakarma So far we have had only two commit styles, COMMIT_LEGACY and COMMIT_UNIVERSAL. This patch adds another commit style COMMIT_ATOMIC which makes use of drmModeAtomicCommit() v2: (Marius)

Re: [Intel-gfx] [PATCH i-g-t v7] lib/igt_kms: Add COMMIT_ATOMIC to igt_display_commit2()

Hi Lionel, I've incorporated your comments using the diff patch submitted by Maarten and submitted the changes https://patchwork.freedesktop.org/series/4274/ Also, please find my comments inline Regards, Mayuresh On 3/8/2016 9:41 PM, Lionel Landwerlin wrote: Hi Maarten, Yeah that would

Re: [Intel-gfx] [PATCH v4] drm/i915: Support to enable TRTT on GEN9

Hi Akash, [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on next-20160309] [cannot apply to v4.5-rc7] [if your patch is applied to the wrong git tree, please drop us a note to help improving the system] url: https://github.com/0day-ci/linux/commits/akash-goel

Re: [Intel-gfx] [PATCH v4] drm/i915: Support to enable TRTT on GEN9

On 3/9/2016 5:34 PM, Chris Wilson wrote: On Wed, Mar 09, 2016 at 05:00:24PM +0530, akash.g...@intel.com wrote: +static int +intel_context_get_trtt(struct intel_context *ctx, + struct drm_i915_gem_context_param *args) +{ + struct drm_i915_gem_context_trtt_param

Re: [Intel-gfx] [PATCH] drm/i915/gen9: add WaClearFlowControlGpgpuContextSave

Hi Tim, [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on v4.5-rc7 next-20160309] [if your patch is applied to the wrong git tree, please drop us a note to help improving the system] url: https://github.com/0day-ci/linux/commits/tim-gore-intel-com/drm-i915-gen9

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gen9: add WaClearFlowControlGpgpuContextSave

== Series Details == Series: drm/i915/gen9: add WaClearFlowControlGpgpuContextSave URL : https://patchwork.freedesktop.org/series/4272/ State : failure == Summary == CC [M] drivers/net/ethernet/smsc/smsc9420.o CC [M] drivers/net/usb/smsc95xx.o LD [M]

Re: [Intel-gfx] [PATCH v4] drm/i915: Support to enable TRTT on GEN9

On Wed, Mar 09, 2016 at 08:20:07PM +0530, Goel, Akash wrote: > >What locks are we holding here? > > > >>+ else if (args->size < sizeof(trtt_params)) > >>+ return -EINVAL; > >>+ else if (copy_from_user(_params, > >>+ to_user_ptr(args->value), > >>+

Re: [Intel-gfx] [PATCH 1/4] drm/i915: Actually retry with bit-banging after GMBUS timeout

On Mon, Mar 07, 2016 at 07:06:37PM +0200, Jani Nikula wrote: > On Mon, 07 Mar 2016, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > After the GMBUS transfer times out, we set force_bit=1 and > > return -EAGAIN expecting the i2c core to call the

Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: GMBUS fixes and whatnot

On Tue, Mar 08, 2016 at 07:25:05AM -, Patchwork wrote: > == Series Details == > > Series: drm/i915: GMBUS fixes and whatnot > URL : https://patchwork.freedesktop.org/series/4178/ > State : warning > > == Summary == > > Series 4178v1 drm/i915: GMBUS fixes and whatnot >

[Intel-gfx] [PATCH i-g-t] igt/kms_rotation_crc: exercise invalid rotations

Add expect-to-fail tests for invalid rotations on each of the plane types. Cc: Joonas Lahtinen Signed-off-by: Matthew Auld --- tests/kms_rotation_crc.c | 96 1 file changed, 96

Re: [Intel-gfx] [PATCH i-g-t] igt/kms_rotation_crc: exercise invalid rotations

On Wed, Mar 09, 2016 at 03:05:24PM +, Matthew Auld wrote: > Add expect-to-fail tests for invalid rotations on each of the plane types. > > Cc: Joonas Lahtinen > Signed-off-by: Matthew Auld > --- > tests/kms_rotation_crc.c | 96 >

[Intel-gfx] [PATCH 2/7] drm/i915: Move laod time PCH detect, DPIO, power domain SW init earlier

These are all SW only init steps, so we can move them earlier. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/i915_dma.c | 12 +--- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c

Re: [Intel-gfx] [PATCH 5/7] drm/i915: Move load time clock gating callback init earlier

On ke, 2016-03-09 at 15:57 +, Chris Wilson wrote: > On Wed, Mar 09, 2016 at 05:31:44PM +0200, Imre Deak wrote: > > Split out the part initing the clock gating callbacks and move it > > earlier. > > > > The rest of the callbacks in intel_init_pm() should be inited in > > the > > same way, but

Re: [Intel-gfx] [PATCH 0/7] drm/i915: Move some load time init steps earlier

On Wed, Mar 09, 2016 at 05:31:39PM +0200, Imre Deak wrote: > While working on the CDCLK init code I realized that the driver load time > dependencies between the different init steps are rather difficult to follow > and so it's not obvious where some new piece of initialization needs to be >

[Intel-gfx] [PATCH v2] drm/i915/gen9: add WaClearFlowControlGpgpuContextSave

From: Tim Gore This allows writes to EU flow control registers. Together with SIP code from the user-mode driver this resolves a hang seen in some pre-emption scenarios. Note that this patch is just the kernel mode part of this workaround. v2. Oops, add FLOW_CONTROL_ENABLE

Re: [Intel-gfx] [PATCH i-g-t v7] lib/igt_kms: Add COMMIT_ATOMIC to igt_display_commit2()

Thanks, It seems the igt_atomic_prepare_plane_commit() function still needs to reset the plane->rotation_changed field (it was at the bottom of my previous email, sorry for that). The way supported property ids are listed from the driver isn't different in the atomic and non atomic cases. The

Re: [Intel-gfx] [PATCH 5/7] drm/i915: Move load time clock gating callback init earlier

On Wed, Mar 09, 2016 at 06:01:32PM +0200, Imre Deak wrote: > > else > > MISSING_CASE() > > > > We definitely need a warning here in case we fall through and leave a > > most unexpected NULL pointer. > > Ok, can add that. At least SKL doesn't have a callback, but I can check > for such platforms

Re: [Intel-gfx] [PATCH v4] drm/i915: Support to enable TRTT on GEN9

On Wed, Mar 09, 2016 at 09:26:08PM +0530, Goel, Akash wrote: > > > On 3/9/2016 8:32 PM, Chris Wilson wrote: > >On Wed, Mar 09, 2016 at 08:20:07PM +0530, Goel, Akash wrote: > >>>What locks are we holding here? > >>> > + else if (args->size < sizeof(trtt_params)) > + return

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Move some load time init steps earlier

== Series Details == Series: drm/i915: Move some load time init steps earlier URL : https://patchwork.freedesktop.org/series/4277/ State : warning == Summary == Series 4277v1 drm/i915: Move some load time init steps earlier

[Intel-gfx] [PATCH v5] intel: New libdrm interface to create unbound wc user mappings for objects

From: Akash Goel A new libdrm interface 'drm_intel_gem_bo_map_wc' is provided by this patch. Through this interface Gfx clients can create write combining virtual mappings of the Gem object. It will provide the same funtionality of 'mmap_gtt' interface without the

Re: [Intel-gfx] [PATCH] drm/i915/bxt: add missing DSI power domain to power well 1

On Tue, 08 Mar 2016, Ville Syrjälä wrote: > On Tue, Mar 08, 2016 at 09:00:56PM +0200, Jani Nikula wrote: >> The DSI power domain was missing from BXT power well 1 definitions, >> failing to get the power well for DSI transcoders. As pipe A is in the >> same power

[Intel-gfx] ✗ Fi.CI.BAT: failure for Add support for GuC-based SLPC (rev2)

== Series Details == Series: Add support for GuC-based SLPC (rev2) URL : https://patchwork.freedesktop.org/series/2691/ State : failure == Summary == Series 2691v2 Add support for GuC-based SLPC http://patchwork.freedesktop.org/api/1.0/series/2691/revisions/2/mbox/ Test drv_getparams_basic:

[Intel-gfx] [PATCH 1/2] drm/i915: Remove some post-commit members from intel_crtc->atomic, v3.

fb_bits is useful to have in the crtc_state for cs flips when the code is updated to use intel_frontbuffer_flip_prepare/complete. So calculate it in advance and move it to crtc_state. The other stuff can be calculated in post_plane_update, and aren't useful elsewhere. Changes since v1: - Changing

[Intel-gfx] [PATCH 2/2] drm/i915: Nuke fbc members from intel_crtc->atomic, v4.

Whenever there's an update to the primary plane, fbc_pre_update and fbc_post_update are called. Kill off intel_crtc->atomic.update_fbc and now that intel_crtc->atomic is empty, kill it off too. Changes since v1: - Add a intel_fbc_supports_rotation helper. Changes since v2: - Remove

Re: [Intel-gfx] [PATCH 13/13] drm/i915: Make SKL/KBL DPLL0 managed by the shared dpll code

Op 08-03-16 om 16:46 schreef Ander Conselvan de Oliveira: > Include DPLL0 in the managed dplls for SKL/KBL. While it has to be kept > enabled because of it driving CDCLK, it is better to special case that > inside the DPLL code than in the higher level. > > v2: Use INTEL_DPLL_ALWAYS_ON flag.

Re: [Intel-gfx] [PATCH i-g-t] [Intel-gfx, v2] tests/gem_buffered_svm: Buffered SVM tests

On Tue, Mar 08, 2016 at 09:58:13AM -0800, Vinay Belgaumkar wrote: > These tests were initially reviewed/merged under the gem_softpin title. > They use softpinning and userptr mechanism to share buffers between > CPU and GPU. > > The userptr part was decoupled from them recently. Adding these

[Intel-gfx] [PULL] topic/drm-misc

Hi Dave, I expect this to be the final drm-misc pull for 4.6: - color manager core patch from Lionel - i915 side is ready too, but will only land in 4.7, but I figured it's better to land this earlier for better coordination with other plane stuff (like alpha/blending) going on. - more

Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for Shared pll improvements (rev4)

On Tue, 2016-03-08 at 16:01 +, Patchwork wrote: > == Series Details == > > Series: Shared pll improvements (rev4) > URL : https://patchwork.freedesktop.org/series/3850/ > State : warning > > == Summary == > > Series 3850v4 Shared pll improvements >

Re: [Intel-gfx] [PATCH 13/13] drm/i915: Make SKL/KBL DPLL0 managed by the shared dpll code

On Wed, 2016-03-09 at 09:36 +0100, Maarten Lankhorst wrote: > Op 08-03-16 om 16:46 schreef Ander Conselvan de Oliveira: > > Include DPLL0 in the managed dplls for SKL/KBL. While it has to be kept > > enabled because of it driving CDCLK, it is better to special case that > > inside the DPLL code