Op 25-04-16 om 18:26 schreef Lionel Landwerlin:
> On 19/04/16 08:52, Maarten Lankhorst wrote:
>> All of intel_post_plane_update is handled there now, so move it over.
>> This is run after the hw state checker because it can't handle checking
>> crtc's separately yet.
>>
>> Signed-off-by: Maarten La
== Series Details ==
Series: series starting with [v4,01/25] drm/i915/fbdev: Call
intel_unpin_fb_obj() on release
URL : https://patchwork.freedesktop.org/series/6310/
State : failure
== Summary ==
Series 6310v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/6310/r
On 25/04/16 16:48, Chris Wilson wrote:
On Mon, Apr 25, 2016 at 04:21:58PM +0100, Dave Gordon wrote:
On 24/04/16 19:10, Chris Wilson wrote:
Rather than reuse the current location of the context in the global GTT
for its hardware identifier, use the context's unique ID assigned to it
for its whol
Imre Deak writes:
> [ text/plain ]
> No need for hard-coding the register value, the corresponding fields are
> defined properly in BSpec.
>
> No functional change.
>
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 ++-
> drivers/gpu/drm/i915/intel_pm.c | 3 ++-
> 2 files
On Tue, Apr 26, 2016 at 07:27:25AM -, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v4,01/25] drm/i915/fbdev: Call
> intel_unpin_fb_obj() on release
> URL : https://patchwork.freedesktop.org/series/6310/
> State : failure
>
> == Summary ==
>
> Series 6310v1 Ser
On Tue, Apr 26, 2016 at 09:06:00AM +0100, Dave Gordon wrote:
> On 25/04/16 16:48, Chris Wilson wrote:
> >On Mon, Apr 25, 2016 at 04:21:58PM +0100, Dave Gordon wrote:
> >>On 24/04/16 19:10, Chris Wilson wrote:
> >>>Rather than reuse the current location of the context in the global GTT
> >>>for its
On 25/04/16 11:39, Chris Wilson wrote:
On Mon, Apr 25, 2016 at 11:07:13AM +0100, Dave Gordon wrote:
On 22/04/16 19:45, Chris Wilson wrote:
On Fri, Apr 22, 2016 at 07:22:55PM +0100, Dave Gordon wrote:
This patch simply changes the default value of "enable_guc_submission"
>from 0 (never) to -1
On ti, 2016-04-26 at 11:11 +0300, Mika Kuoppala wrote:
> Imre Deak writes:
>
> > [ text/plain ]
> > No need for hard-coding the register value, the corresponding
> > fields are
> > defined properly in BSpec.
> >
> > No functional change.
> >
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gp
If we are not in FULL_48BIT_PPGTT mode then we really shouldn't
continue on with our allocations, given that the call to free_pdp would
bail early without freeing everything, thus leaking memory.
v2:
(Joonas Lahtinen)
- tidy up with goto teardown path
v3:
(Joonas Lahtinen)
- use more appropria
This patch resizes the GuC WOPCM to so that the GuC and the RC6 memory
spaces do not overlap.
Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
Signed-off-by: Peter Antoine
---
drivers/gpu/drm/i915/i915_guc_reg.h | 5 +++--
drivers/gpu/drm/i915/intel_guc_loader.c | 6 +-
2 files c
On ti, 2016-04-26 at 12:03 +0300, Imre Deak wrote:
> On ti, 2016-04-26 at 11:11 +0300, Mika Kuoppala wrote:
> > Imre Deak writes:
> >
> > > [ text/plain ]
> > > No need for hard-coding the register value, the corresponding
> > > fields are
> > > defined properly in BSpec.
> > >
> > > No function
The teardown path in render_state_init leaves so->obj != NULL.
Suggested-by: Joonas Lahtinen
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_render_state.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c
b/drivers/gpu/drm/i915/i915
Use goto teardown path and also ensure we reset any struct members which
would otherwise contain an error encoded pointer, and could be mistaken
for a valid address.
Cc: Joonas Lahtinen
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 36 +---
On Tue, Apr 26, 2016 at 10:08:07AM +0100, Matthew Auld wrote:
> If we are not in FULL_48BIT_PPGTT mode then we really shouldn't
> continue on with our allocations, given that the call to free_pdp would
> bail early without freeing everything, thus leaking memory.
Why? Why are you second guessing t
From: Damien Lespiau
We'd like to be able to program the blending modes of display planes.
Ville suggested to use something similar to the GL blend states, which
does seem like a good idea.
For now, we only consider blend factors, but room is left for
extensions: blend equation, separate rgb/alp
From: Damien Lespiau
This patch adds the blend functions, and as per the
blend function, updates the plane control register values
V2: Add blend support for all RGB formats
Fix the reg writes on plane_ctl_alpha bits.
V3: Add support support for primary and cursor planes.
fix an issue where
From: vandita kulkarni
The below patches support plane and pixel blending
by adding two properties blend_func and blend_color.
As per Damien's initial patches, this design based on
OpenGL's blend equations is suggested by Ville.
All the below patches are tested on BXT android platform.
V2: Squa
From: Damien Lespiau
Add blend color property and update the
documentation for the same
V2: Add blend color support in get property.
Signed-off-by: Damien Lespiau
Signed-off-by: vandita kulkarni
---
Documentation/DocBook/gpu.tmpl | 11 +--
drivers/gpu/drm/drm_atomic.c | 4
dr
From: Damien Lespiau
In the hope of expressing colors in the KMS API in a consitant want,
let's introduce a ARGB 16161616 color and a few convinience macros
around it.
Signed-off-by: Damien Lespiau
---
include/uapi/drm/drm_mode.h | 34 ++
1 file changed, 34 inse
From: Damien Lespiau
This patch adds support for blending modes involving
color.
V2: Add support for primary plane.
Separate out plane alpha disable functionality from per pixel
drop_alpha blend function and add another blend function case for
disabling plane alpha.
Signed-off-by: Damien Lespia
On Mon, Apr 25, 2016 at 03:51:09PM +0100, Tvrtko Ursulin wrote:
>
> On 25/04/16 11:35, Ankitprasad Sharma wrote:
> >On Thu, 2016-04-21 at 15:59 +0100, Tvrtko Ursulin wrote:
> >>On 21/04/16 15:46, Chris Wilson wrote:
> >>>On Thu, Apr 21, 2016 at 03:04:52PM +0100, Tvrtko Ursulin wrote:
>
>
On 26/04/16 09:49, Dave Gordon wrote:
On 25/04/16 11:39, Chris Wilson wrote:
On Mon, Apr 25, 2016 at 11:07:13AM +0100, Dave Gordon wrote:
On 22/04/16 19:45, Chris Wilson wrote:
[snip]
And what exactly is that atomic64_cmpxchg() serialising with? There are
no other CPUs contending with the w
== Series Details ==
Series: drm/i915: bail in alloc_pdp when !FULL_48BIT_PPGTT
URL : https://patchwork.freedesktop.org/series/6312/
State : failure
== Summary ==
Series 6312v1 drm/i915: bail in alloc_pdp when !FULL_48BIT_PPGTT
http://patchwork.freedesktop.org/api/1.0/series/6312/revisions/1/m
On 26/04/16 10:21, Matthew Auld wrote:
The teardown path in render_state_init leaves so->obj != NULL.
Suggested-by: Joonas Lahtinen
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_render_state.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_
== Series Details ==
Series: drm/i915: resize the GuC WOPCM for rc6
URL : https://patchwork.freedesktop.org/series/6313/
State : failure
== Summary ==
Series 6313v1 drm/i915: resize the GuC WOPCM for rc6
http://patchwork.freedesktop.org/api/1.0/series/6313/revisions/1/mbox/
Test kms_flip:
On Thu, 07 Apr 2016, Jani Nikula wrote:
> False ideas introduced in
>
> commit 1d96a4a8ace6c1b08c7d203d9533b14e59f2200b
> Author: Jani Nikula
> Date: Fri Mar 18 13:11:10 2016 +0200
>
> drm/i915/dsi: add support for DSI sequence block v2 gpio element
>
> Acked-by: Ville Syrjälä
> Signed-off
Series v5 after [1]. I'll call it *series* v5 because the last one was
v4 although the patches are of all sorts of versions and I've lost
track. The bxt patch is still hacky.
BR,
Jani.
[1] http://mid.gmane.org/cover.1460039033.git.jani.nik...@intel.com
Jani Nikula (3):
drm/i915/dsi: add suppor
Only support NC GPIOs for now, and assume the vlv gpio table only has NC
GPIOs for now.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
b/drivers/gpu/drm/
Add support for CHV gpio programming in DSI gpio elements.
v2: Overhaul macros according to Ville's review.
v3: Address Ville's review:
- swap E and SE gpio ranges
- add a note about max SE index
- use GPO, not HIZ
- swap cfg0 and cfg1
v4: fix port for dsi sequence versions 1 and 2
[Rewritt
On Tue, Apr 26, 2016 at 10:52:41AM +0100, Dave Gordon wrote:
> On 26/04/16 09:49, Dave Gordon wrote:
> >On 25/04/16 11:39, Chris Wilson wrote:
> >>On Mon, Apr 25, 2016 at 11:07:13AM +0100, Dave Gordon wrote:
> >>>On 22/04/16 19:45, Chris Wilson wrote:
>
> [snip]
>
> And what exactly is that a
On 21/04/16 13:05, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
i915_gem_obj_to_vma is one of the most expensive functions in
our profiles. Could avoiding some branching by replacing it
with arithmetic be beneficial? Some benchmarks suggest it
slightly might.
Signed-off-by: Tvrtko Ursulin
---
Request the GPIO by index through the consumer API. For now, use a quick
hack to store the already requested ones, simply because I have no idea
whether this actually works or not, and I have no way to test it.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 28 ++
On Tue, 26 Apr 2016, Patchwork wrote:
== Series Details ==
Series: drm/i915: resize the GuC WOPCM for rc6
URL : https://patchwork.freedesktop.org/series/6313/
State : failure
== Summary ==
Series 6313v1 drm/i915: resize the GuC WOPCM for rc6
http://patchwork.freedesktop.org/api/1.0/series/6
On Tue, Apr 26, 2016 at 11:35:53AM +0100, Dave Gordon wrote:
> On 21/04/16 13:05, Tvrtko Ursulin wrote:
> >From: Tvrtko Ursulin
> >
> >i915_gem_obj_to_vma is one of the most expensive functions in
> >our profiles. Could avoiding some branching by replacing it
> >with arithmetic be beneficial? Some
On Wed, Mar 30, 2016 at 11:43:52AM +0100, Emil Velikov wrote:
> On 30 March 2016 at 10:45, Daniel Vetter wrote:
> > Lots of arm drivers get this wrong and for most arm boards this is the
> > right thing actually. And anyway with most loaders you want to chase
> > sysfs links anyway to figure out w
== Series Details ==
Series: drm/i915: In render_state_init reset obj in teardown path
URL : https://patchwork.freedesktop.org/series/6314/
State : failure
== Summary ==
Series 6314v1 drm/i915: In render_state_init reset obj in teardown path
http://patchwork.freedesktop.org/api/1.0/series/6314
On Wed, Mar 30, 2016 at 11:45:13AM +0200, Daniel Vetter wrote:
> For documentation and paranoia.
>
> Signed-off-by: Daniel Vetter
Merged to drm-misc with Chris' irc ack - we just discussed the opposite
WRITE_ONCE in some other patches.
-Daniel
> ---
> drivers/gpu/drm/drm_sysfs.c | 11 -
These patches add support for Backlight Control using DPCD registers on eDP
displays.
- Patch 1 Adds macro for DPCD registers capability size to drm_dp_helper.h
- Patch 2 Reads the eDP DPCD Display Control capability registers.
- Patch 3 Implements functionaly for DPCD Backlight Control
Yetunde
Add new edp_dpcd variable to intel_dp.
Read and save eDP Display control capability registers to edp_dpcd.
Cc: Jani Nikula
Signed-off-by: Yetunde Adebisi
---
drivers/gpu/drm/i915/intel_dp.c | 15 ++-
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 11 insertions(+), 5 dele
This patch adds support for eDP backlight control using DPCD registers to
backlight hooks in intel_panel.
It checks for backlight control over AUX channel capability and sets up
function pointers to get and set the backlight brightness level if
supported.
v2: Moved backlight functions from intel_
This is used when reading Display Control capability Registers on the sink
device.
cc: Jani Nikula
cc: dri-de...@lists.freedesktop.org
Signed-off-by: Yetunde Adebisi
Reviewed-by: Jani Nikula
---
include/drm/drm_dp_helper.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/drm_dp_
Hello!
I have tried the patch https://patchwork.freedesktop.org/series/4783/ by
compiling manjaro kernel 4.6-rc4 with it, the brightness keys still don't
work on an Asus UX305FA.
FYI, applying the hacky https://bugzilla.kernel.org/attachment.cgi?id=195071
certainly makes them work.
If I can provide
On 25 April 2016 at 17:05, wrote:
> From: Robert Foss
>
> Increase the number of planes supported to 10.
>
> kmstest_plane_name only previously supported 4 planes,
> this patch adds support for up to 10 planes.
>
> Signed-off-by: Robert Foss
> ---
> lib/igt_kms.c | 6 ++
> lib/igt_kms.h |
On 25 April 2016 at 16:35, wrote:
> From: Robert Foss
>
>
> Changes since v1:
> - Squash patches
> - Based patch on
> https://lists.freedesktop.org/archives/intel-gfx/2016-March/090617.html
Thanks for the patches, you can add my Reviewed-by tag to all except
the 6th patch, about which I don't
== Series Details ==
Series: drm/i915: tidy up gen8_init_scratch
URL : https://patchwork.freedesktop.org/series/6315/
State : failure
== Summary ==
Series 6315v1 drm/i915: tidy up gen8_init_scratch
http://patchwork.freedesktop.org/api/1.0/series/6315/revisions/1/mbox/
Test kms_pipe_crc_basic:
On 25 April 2016 at 17:05, wrote:
> From: Robert Foss
>
> Previously crtc0 was statically used for VBLANK tests, but
> that assumption is not valid for the VC4 platform.
> Instead we're now explicitly setting the mode.
>
> Also add support for testing all connected connectors during
> the same t
On Tue, 05 Apr 2016, Yetunde Adebisi wrote:
> These patches add support for Backlight Control using DPCD registers on eDP
> displays.
Pushed to drm-intel-next-queued, thanks for the patches, and, again,
apologies for the way too long delay with getting these merged.
I fixed some whitespace issu
Setting a write-back cache policy in the MOCS entry definition also
implies snooping, which has a considerable overhead. This is
unexpected for a few reasons:
- From user-space's point of view since it didn't want a coherent
surface (it didn't set the buffer as such via the set caching IOCTL).
-
Use named struct initializers for clarity. Also fix the target cache
definition to reflect its role in GEN9 onwards. On GEN8 a TC value of 0
meant ELLC but on GEN9+ it means the TC and LRU controls are taken from
the PTE.
No functional change, igt/gem_mocs_settings still passing after this
change.
Adjust the third MOCS entry value based on the corresponding change in
the kernel.
CC: Chris Wilson
Signed-off-by: Imre Deak
---
tests/gem_mocs_settings.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/gem_mocs_settings.c b/tests/gem_mocs_settings.c
index bc553e9..4fc
On Tue, Apr 26, 2016 at 03:02:59PM +0530, Vandita Kulkarni wrote:
> From: vandita kulkarni
>
> The below patches support plane and pixel blending
> by adding two properties blend_func and blend_color.
> As per Damien's initial patches, this design based on
> OpenGL's blend equations is suggested
On Tue, Apr 26, 2016 at 03:03:00PM +0530, Vandita Kulkarni wrote:
> From: Damien Lespiau
>
> We'd like to be able to program the blending modes of display planes.
> Ville suggested to use something similar to the GL blend states, which
> does seem like a good idea.
>
> For now, we only consider
On Tue, Apr 26, 2016 at 03:03:00PM +0530, Vandita Kulkarni wrote:
> From: Damien Lespiau
>
> We'd like to be able to program the blending modes of display planes.
> Ville suggested to use something similar to the GL blend states, which
> does seem like a good idea.
>
> For now, we only consider
On Wed, 30 Mar 2016, Jani Nikula wrote:
> From: Deepak M
>
> For dual link panel scenarios there are new fields added in the
> VBT which indicate on which port the PWM cntrl and CABC ON/OFF
> commands needs to be sent.
>
> v2: Moving the comment to intel_dsi.h(Jani)
>
> v3: Renaming the field nam
On Mon, Apr 25, 2016 at 02:42:50AM +0300, Kirill A. Shutemov wrote:
> On Mon, Apr 04, 2016 at 02:18:10PM +0100, Chris Wilson wrote:
> > From: Akash Goel
> >
> > This provides support for the drivers or shmem file owners to register
> > a set of callbacks, which can be invoked from the address spa
On Tue, Apr 26, 2016 at 03:44:22PM +0300, Imre Deak wrote:
> Setting a write-back cache policy in the MOCS entry definition also
> implies snooping, which has a considerable overhead. This is
> unexpected for a few reasons:
If it is snooping, then I don't see why it is undesirable to have it
avail
On Tue, Apr 26, 2016 at 03:44:22PM +0300, Imre Deak wrote:
> Setting a write-back cache policy in the MOCS entry definition also
> implies snooping, which has a considerable overhead. This is
> unexpected for a few reasons:
> - From user-space's point of view since it didn't want a coherent
> sur
Next version of [1].
BR,
Jani.
[1] http://mid.gmane.org/1459346623-30752-1-git-send-email-jani.nik...@intel.com
Deepak M (2):
drm/i915: Parse LFP brightness control field in VBT
CABC support for Panel PWM backlight control
Jani Nikula (1):
drm/i915: Add DCS control for Panel PWM
drivers
From: Deepak M
These fields in VBT indicates the PWM source which
is used and also the controller number.
v2 by Jani: check for out of bounds access, some renames, change default
type, etc.
v3 by Jani: s/INTEL_BACKLIGHT_CABC/INTEL_BACKLIGHT_DSI_DCS/
Signed-off-by: Deepak M
Signed-off-by: Jani
If the source of the backlight PWM is from the
panel then the PWM can be controlled by DCS
command, this patch adds the support to
enable/disbale panel PWM, control backlight level
etc...
v2: Moving the CABC bkl functions to new file.(Jani)
v3: Rebase
v4: Rebase
v5: Use mipi_dsi_dcs_write() ins
From: Deepak M
In CABC (Content Adaptive Brightness Control) content grey level
scale can be increased while simultaneously decreasing
brightness of the backlight to achieve same perceived brightness.
The CABC is not standardized and panel vendors are free to follow
their implementation. The CAB
On ti, 2016-04-26 at 13:57 +0100, Chris Wilson wrote:
> On Tue, Apr 26, 2016 at 03:44:22PM +0300, Imre Deak wrote:
> > Setting a write-back cache policy in the MOCS entry definition also
> > implies snooping, which has a considerable overhead. This is
> > unexpected for a few reasons:
>
> If it is
On Mon, Apr 25, 2016 at 10:54:27AM +0100, Chris Wilson wrote:
> > As each batch buffer completes, it raises an interrupt which wakes up
> > the scheduler. Note that it is possible for multiple buffers to
> > complete before the IRQ handler gets to run. Further, the seqno values
> > of the individua
On Tue, Apr 26, 2016 at 04:17:55PM +0300, Imre Deak wrote:
> On ti, 2016-04-26 at 13:57 +0100, Chris Wilson wrote:
> > On Tue, Apr 26, 2016 at 03:44:22PM +0300, Imre Deak wrote:
> > > Setting a write-back cache policy in the MOCS entry definition also
> > > implies snooping, which has a considerabl
On Fri, Apr 22, 2016 at 02:27:28PM +0100, Lionel Landwerlin wrote:
> On 22/04/16 13:59, Daniel Vetter wrote:
> >On Thu, Apr 21, 2016 at 05:01:31PM +0100, Lionel Landwerlin wrote:
> >>It seems we don't have a test verifying events with atomic commits
> >>yet. Here is a first step.
> >>
> >>Cc: Maart
On 26/04/16 11:35, Chris Wilson wrote:
On Tue, Apr 26, 2016 at 10:52:41AM +0100, Dave Gordon wrote:
On 26/04/16 09:49, Dave Gordon wrote:
On 25/04/16 11:39, Chris Wilson wrote:
On Mon, Apr 25, 2016 at 11:07:13AM +0100, Dave Gordon wrote:
On 22/04/16 19:45, Chris Wilson wrote:
[snip]
And w
On ti, 2016-04-26 at 14:23 +0100, Chris Wilson wrote:
> On Tue, Apr 26, 2016 at 04:17:55PM +0300, Imre Deak wrote:
> > On ti, 2016-04-26 at 13:57 +0100, Chris Wilson wrote:
> > > On Tue, Apr 26, 2016 at 03:44:22PM +0300, Imre Deak wrote:
> > > > Setting a write-back cache policy in the MOCS entry d
On Fri, Apr 22, 2016 at 09:54:51AM -0400, robert.f...@collabora.com wrote:
> From: Robert Foss
>
> Makes sure we automatically extend that when adding more planes.
> Inspired by a patch from Robert Foss who extended the max, but forgot
> all about the enum.
>
> While at it, also fix up the white
== Series Details ==
Series: series starting with [PATCHv2,1/5] drm: Introduce the blend-func
property
URL : https://patchwork.freedesktop.org/series/6316/
State : warning
== Summary ==
Series 6316v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/6316/revisions/1/
On Mon, Apr 25, 2016 at 08:12:41PM +, Zanoni, Paulo R wrote:
> One of the things about our driver is that it tries to be very very
> conservative regarding the eDP timings, leading to waits longer than
> necessary for pretty much everyone. We tried to optimize this in the
> past, but due to the
On Fri, Apr 22, 2016 at 09:54:50AM -0400, robert.f...@collabora.com wrote:
> From: Robert Foss
>
> Changes since v1:
> - Removed un-used members of data_t struct in kms_vblank.c.
> - Renamed plane_counter to n_planes.
> - Removed un-needed handling CURSOR plane location.
> - Added names for addit
On Mon, Apr 25, 2016 at 09:29:42AM +0100, Chris Wilson wrote:
> On Mon, Apr 25, 2016 at 08:31:07AM +0100, Dave Gordon wrote:
> > On 22/04/16 19:51, Chris Wilson wrote:
> > >On Fri, Apr 22, 2016 at 07:45:15PM +0100, Chris Wilson wrote:
> > >>On Fri, Apr 22, 2016 at 07:22:55PM +0100, Dave Gordon wrot
On Tue, Apr 26, 2016 at 04:43:10PM +0300, Imre Deak wrote:
> On ti, 2016-04-26 at 14:23 +0100, Chris Wilson wrote:
> > On Tue, Apr 26, 2016 at 04:17:55PM +0300, Imre Deak wrote:
> > > On ti, 2016-04-26 at 13:57 +0100, Chris Wilson wrote:
> > > > On Tue, Apr 26, 2016 at 03:44:22PM +0300, Imre Deak w
On Fri, Apr 22, 2016 at 05:25:00PM -0400, robert.f...@collabora.com wrote:
> From: Robert Foss
>
> Add support for DRM_MODE_CONNECTOR_LVDS and DRM_MODE_CONNECTOR_DSI
> connectors.
>
> Signed-off-by: Robert Foss
> ---
> tests/kms_panel_fitting.c | 12 +---
> 1 file changed, 9 insertions
On Sat, Apr 23, 2016 at 12:05:44AM +0530, akash.g...@intel.com wrote:
> From: Akash Goel
>
> Added a new GT_PM_INTERVAL_TO_US macro to perform the platform
> specific conversion of PM time interval values to microseconds unit.
>
> Reviewed-by: Chris Wilson
> Signed-off-by: Akash Goel
> ---
>
The async name is deprecated and should be changed to nonblocking.
Cc: Thierry Reding
Cc: "Terje Bergström"
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/tegra/drm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/t
The async name is deprecated and should be changed to nonblocking.
Cc: Liviu Dudau
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/arm/hdlcd_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/arm/hdlcd_drv.c b/drivers/gpu/drm/arm/hdlcd_drv.c
index 3ac
Hi,
On 26.04.2016 16:23, Chris Wilson wrote:
On Tue, Apr 26, 2016 at 04:17:55PM +0300, Imre Deak wrote:
On ti, 2016-04-26 at 13:57 +0100, Chris Wilson wrote:
On Tue, Apr 26, 2016 at 03:44:22PM +0300, Imre Deak wrote:
Setting a write-back cache policy in the MOCS entry definition also
implies
This is the first step of renaming async commit to nonblocking commit.
The flag passed by userspace is NONBLOCKING, and async has a different
meaning for page flips, where it means as soon as possible.
Fixing up comments in drm core is done manually, to make sure I didn't
miss anything.
For drive
The async name is deprecated and should be changed to nonblocking.
Cc: Inki Dae
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/exynos/exynos_drm_drv.c | 4 ++--
drivers/gpu/drm/exynos/exynos_drm_drv.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/e
The async name is deprecated and should be changed to nonblocking.
Also comments seem to be a bit outdated, as it looks like
nonblocking commit is supported by msm.
Cc: Rob Clark
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/msm/msm_atomic.c | 9 -
drivers/gpu/drm/msm/msm_drv.h
The async name is deprecated and should be changed to nonblocking.
Cc: Laurent Pinchart
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/rcar-du/rcar_du_kms.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
b/drivers/gpu/drm/rc
The async name is deprecated and should be changed to nonblocking.
Cc: Mark Yao
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c
b/drivers/gpu/drm
On Fri, Apr 22, 2016 at 05:24:53PM -0400, robert.f...@collabora.com wrote:
> From: Robert Foss
>
> This series removes some dead code from kms_panel_fitting and
> enables support for LVDS and DSI connectors.
>
> Robert Foss (7):
> kms_panel_fitting: Remove un-read variable.
> kms_panel_fitti
Another step in renaming async to nonblocking for atomic commit.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/drm_atomic.c| 12 ++--
drivers/gpu/drm/drm_atomic_helper.c | 4 ++--
include/drm/drm_atomic.h| 2 +-
3 files changed, 9 insertions(+), 9 deletions(-
Userspace calls the atomic ioctl with DRM_MODE_ATOMIC_NONBLOCK
when it doesn't want the ioctl to block for completion.
In the kernel it's called async commit, which is confusing. The legacy
pageflip and atomic ioctl also have a flag DRM_MODE_PAGE_FLIP_ASYNC
which means that the flip should happen
The async name is deprecated and should be changed to nonblocking.
Cc: Tomi Valkeinen
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/omapdrm/omap_drv.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c
b/drivers/gpu/drm/omapdrm/oma
The async name is deprecated and should be changed to nonblocking.
Cc: Benjamin Gaignard
Cc: Vincent Abriou
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/sti/sti_drv.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/sti/sti_drv.c b/drivers/gpu/d
The async name is deprecated and should be changed to nonblocking.
Cc: Eric Anholt
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/vc4/vc4_kms.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index 471
The async name is deprecated and should be changed to nonblocking.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_dis
Hello!
I have tried the patch https://patchwork.freedesktop.org/series/4783/ by
compiling manjaro kernel 4.6-rc4 with it, the brightness keys still don't
work on an Asus UX305FA.
FYI, applying the hacky https://bugzilla.kernel.org/attachment.cgi?id=195071
certainly makes them work.
If I can provide
Hi,
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v4.6-rc5 next-20160426]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Jani-Nikula/drm-i915-dsi-dcs-backlight-control
On Fri, Apr 22, 2016 at 05:24:59PM -0400, robert.f...@collabora.com wrote:
> From: Robert Foss
>
> If an incompatible connector is found, don't skip the test,
> but rather keep looking for valid connectors.
>
> Signed-off-by: Robert Foss
> ---
> tests/kms_panel_fitting.c | 5 +++--
> 1 file ch
On Mon, Apr 25, 2016 at 03:37:11PM +0100, Dave Gordon wrote:
> Split the function of "enable_guc_submission" into two separate
> options. The new one ("enable_guc_loading") controls only the
> *fetching and loading* of the GuC firmware image. The existing
> one is redefined to control only the *us
On Tue, Apr 26, 2016 at 11:38:46AM +0100, Peter Antoine wrote:
> On Tue, 26 Apr 2016, Patchwork wrote:
>
> >== Series Details ==
> >
> >Series: drm/i915: resize the GuC WOPCM for rc6
> >URL : https://patchwork.freedesktop.org/series/6313/
> >State : failure
> >
> >== Summary ==
> >
> >Series 631
On Tue, Apr 26, 2016 at 01:27:39PM +0300, Jani Nikula wrote:
> Only support NC GPIOs for now, and assume the vlv gpio table only has NC
> GPIOs for now.
What is an "NC"? I think at least the commit message should explain that,
maybe even the code ...
-Daniel
>
> Signed-off-by: Jani Nikula
> ---
Hi,
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v4.6-rc5 next-20160426]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Jani-Nikula/drm-i915-dsi-dcs-backlight-control
igt_fork_hang_detector() was called from a igt_fixture block, while its
counterpart (igt_stop_hang_detector) was called normally, causing
SIGTERM to be sent when running under check target.
Signed-off-by: Marius Vlad
---
tests/gem_close_race.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion
== Series Details ==
Series: drm/i915/dsi: improved gpio element support for vlv/chv/bxt (rev5)
URL : https://patchwork.freedesktop.org/series/4625/
State : success
== Summary ==
Series 4625v5 drm/i915/dsi: improved gpio element support for vlv/chv/bxt
http://patchwork.freedesktop.org/api/1.0/
On Tue, Apr 26, 2016 at 04:11:33PM +0200, Maarten Lankhorst wrote:
> Userspace calls the atomic ioctl with DRM_MODE_ATOMIC_NONBLOCK
> when it doesn't want the ioctl to block for completion.
>
> In the kernel it's called async commit, which is confusing. The legacy
> pageflip and atomic ioctl also
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