[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/guc: Sanitory checks for platform that dont have GuC

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Sanitory checks for platform that dont have GuC
URL   : https://patchwork.freedesktop.org/series/13358/
State : failure

== Summary ==

Series 13358v1 drm/i915/guc: Sanitory checks for platform that dont have GuC
https://patchwork.freedesktop.org/api/1.0/series/13358/revisions/1/mbox/

Test gem_busy:
Subgroup basic-hang-default:
pass   -> FAIL   (fi-hsw-4770r)
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> DMESG-WARN (fi-skl-6770hq)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-byt-j1900)
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS   (fi-byt-j1900)

fi-bdw-5557u total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050 total:244  pass:202  dwarn:0   dfail:0   fail:0   skip:42 
fi-bxt-t5700 total:244  pass:214  dwarn:0   dfail:0   fail:0   skip:30 
fi-byt-j1900 total:244  pass:212  dwarn:0   dfail:0   fail:1   skip:31 
fi-byt-n2820 total:244  pass:208  dwarn:0   dfail:0   fail:1   skip:35 
fi-hsw-4770  total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-hsw-4770r total:244  pass:221  dwarn:0   dfail:0   fail:1   skip:22 
fi-ilk-650   total:244  pass:182  dwarn:0   dfail:0   fail:2   skip:60 
fi-ivb-3520m total:244  pass:219  dwarn:0   dfail:0   fail:0   skip:25 
fi-ivb-3770  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 
fi-kbl-7200u total:244  pass:220  dwarn:0   dfail:0   fail:0   skip:24 
fi-skl-6260u total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hqtotal:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-skl-6700k total:244  pass:219  dwarn:1   dfail:0   fail:0   skip:24 
fi-skl-6770hqtotal:244  pass:227  dwarn:2   dfail:0   fail:1   skip:14 
fi-snb-2520m total:244  pass:208  dwarn:0   dfail:0   fail:0   skip:36 
fi-snb-2600  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 

Results at /archive/results/CI_IGT_test/Patchwork_2634/

2dff18acaa95a26b882a5f9910d7ded514f18415 drm-intel-nightly: 
2016y-10m-05d-13h-58m-08s UTC integration manifest
0484c38 drm/i915/guc: Sanitory checks for platform that dont have GuC

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Re: [Intel-gfx] [PATCH 2/2] drm/i915: KBL - Recommended buffer translation programming for DisplayPort

[Vivi, Rodrigo]

On Tue, 2016-10-04 at 10:05 +0300, Jani Nikula wrote:
> On Tue, 04 Oct 2016, "Vivi, Rodrigo"  wrote:
> > On Mon, 2016-10-03 at 13:50 +0300, Jani Nikula wrote:
> >> On Fri, 30 Sep 2016, Rodrigo Vivi  wrote:
> >> > According to spec: "KBL re-uses SKL values, except where
> >> > specific KBL values are listed."
> >> >
> >> > And recently spec has changed adding different table for Display Port 
> >> > only.
> >> > But for all SKUs (H,S,U,Y) we have slightly different values.
> >> >
> >> > Cc: Manasi Navare 
> >> > Cc: Arthur Runyan 
> >> > Signed-off-by: Rodrigo Vivi 
> >> > ---
> >> >  drivers/gpu/drm/i915/intel_ddi.c | 88 
> >> > +++-
> >> >  1 file changed, 78 insertions(+), 10 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> >> > b/drivers/gpu/drm/i915/intel_ddi.c
> >> > index 018964b..1573360 100644
> >> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> >> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> >> > @@ -167,8 +167,47 @@ static const struct ddi_buf_trans 
> >> > skl_y_ddi_translations_dp[] = {
> >> >  { 0x80005012, 0x00C0, 0x3 },
> >> >  };
> >> >  
> >> > +/* Kabylake H and S */
> >> > +static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
> >> > +{ 0x2016, 0x00A0, 0x0 },
> >> > +{ 0x5012, 0x009B, 0x0 },
> >> > +{ 0x7011, 0x0088, 0x0 },
> >> > +{ 0x80009010, 0x00C0, 0x1 },
> >> > +{ 0x2016, 0x009B, 0x0 },
> >> > +{ 0x5012, 0x0088, 0x0 },
> >> > +{ 0x80007011, 0x00C0, 0x1 },
> >> > +{ 0x2016, 0x009F, 0x0 },
> >> > +{ 0x80005012, 0x00C0, 0x1 },
> >> > +};
> >> > +
> >> > +/* Kabylake U */
> >> > +static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
> >> > +{ 0x201B, 0x00A1, 0x0 },
> >> > +{ 0x5012, 0x0088, 0x0 },
> >> > +{ 0x80007011, 0x00CD, 0x3 },
> >> > +{ 0x80009010, 0x00C0, 0x3 },
> >> > +{ 0x201B, 0x009D, 0x0 },
> >> > +{ 0x80005012, 0x00C0, 0x3 },
> >> > +{ 0x80007011, 0x00C0, 0x3 },
> >> > +{ 0x2016, 0x004F, 0x0 },
> >> > +{ 0x80005012, 0x00C0, 0x3 },
> >> > +};
> >> > +
> >> > +/* Kabylake Y */
> >> > +static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
> >> > +{ 0x1017, 0x00A1, 0x0 },
> >> > +{ 0x5012, 0x0088, 0x0 },
> >> > +{ 0x80007011, 0x00CD, 0x3 },
> >> > +{ 0x8000800F, 0x00C0, 0x3 },
> >> > +{ 0x1017, 0x009D, 0x0 },
> >> > +{ 0x80005012, 0x00C0, 0x3 },
> >> > +{ 0x80007011, 0x00C0, 0x3 },
> >> > +{ 0x1017, 0x004C, 0x0 },
> >> > +{ 0x80005012, 0x00C0, 0x3 },
> >> > +};
> >> > +
> >> >  /*
> >> > - * Skylake H and S
> >> > + * Skylake/Kabylake H and S
> >> >   * eDP 1.4 low vswing translation parameters
> >> >   */
> >> >  static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
> >> > @@ -185,7 +224,7 @@ static const struct ddi_buf_trans 
> >> > skl_ddi_translations_edp[] = {
> >> >  };
> >> >  
> >> >  /*
> >> > - * Skylake U
> >> > + * Skylake/Kabylake U
> >> >   * eDP 1.4 low vswing translation parameters
> >> >   */
> >> >  static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
> >> > @@ -202,7 +241,7 @@ static const struct ddi_buf_trans 
> >> > skl_u_ddi_translations_edp[] = {
> >> >  };
> >> >  
> >> >  /*
> >> > - * Skylake Y
> >> > + * Skylake/Kabylake Y
> >> >   * eDP 1.4 low vswing translation parameters
> >> >   */
> >> >  static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
> >> > @@ -218,7 +257,7 @@ static const struct ddi_buf_trans 
> >> > skl_y_ddi_translations_edp[] = {
> >> >  { 0x0018, 0x008A, 0x0 },
> >> >  };
> >> >  
> >> > -/* Skylake U, H and S */
> >> > +/* Skylake/Kabylake U, H and S */
> >> >  static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
> >> >  { 0x0018, 0x00AC, 0x0 },
> >> >  { 0x5012, 0x009D, 0x0 },
> >> > @@ -233,7 +272,7 @@ static const struct ddi_buf_trans 
> >> > skl_ddi_translations_hdmi[] = {
> >> >  { 0x8018, 0x00C0, 0x1 },
> >> >  };
> >> >  
> >> > -/* Skylake Y */
> >> > +/* Skylake/Kabylake Y */
> >> >  static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
> >> >  { 0x0018, 0x00A1, 0x0 },
> >> >  { 0x5012, 0x00DF, 0x0 },
> >> > @@ -334,10 +373,10 @@ bdw_get_buf_trans_edp(struct drm_i915_private 
> >> > *dev_priv, int *n_entries)
> >> >  static const struct ddi_buf_trans *
> >> >  skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
> >> >  {
> >> > -if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
> >> > +if (IS_SKL_ULX(dev_priv)) {
> >> >  

Re: [Intel-gfx] [PATCH] drm/i915: Don't try to handle GuC when GuC is not supported.

[Vivi, Rodrigo]

Hi Daniel,

So, can we close https://bugs.freedesktop.org/show_bug.cgi?id=97573 with
wontfix or notabug?

I don't have a strong side on that actually, but Jani was against it it
seems.

Thanks,
Rodrigo.

On Wed, 2016-10-05 at 15:50 +0200, Daniel Vetter wrote:
> On Thu, Sep 22, 2016 at 04:55:07PM +, Vivi, Rodrigo wrote:
> > On Wed, 2016-09-21 at 18:00 -0300, Paulo Zanoni wrote:
> > > Em Qua, 2016-09-21 às 11:22 -0700, Rodrigo Vivi escreveu:
> > > > Avoid any kind of GuC handling if GuC is not supported
> > > > on a giving platform.
> > > > 
> > > > Besides being useless handling, our driver needs
> > > > to be smarter than the user trying to use an invalid paramenter.
> > > 
> > > So the problem is when a platform doesn't support guc and the user
> > > passes i915.enable_guc_something=1, right?
> > 
> > 1 is not a problem actually since it means "use if available". There is
> > not firmware and execution continues.
> > 
> > 2 is the problem because it means "use guc or fail if not available".
> > But platforms that don't have guc can't fail. driver needs to be smarter
> > than that.
> 
> Not sure it needs to be smarter than that really, since all these debug
> options auto-taint the kernel if you touch them. As in: You get to keep
> all the pieces.
> 
> We can still do some auto-cleanup of modoptions ofc if there's a good need
> for them.
> -Daniel
> 
> > 
> > > 
> > > > 
> > > > Cc: Jani Nikula 
> > > > Cc: Anusha Srivatsa 
> > > > Cc: Christophe Prigent 
> > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97573
> > > > Signed-off-by: Rodrigo Vivi 
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_guc_loader.c | 7 +++
> > > >  1 file changed, 7 insertions(+)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
> > > > b/drivers/gpu/drm/i915/intel_guc_loader.c
> > > > index 6fd39ef..da0f5ed 100644
> > > > --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> > > > +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> > > > @@ -720,6 +720,13 @@ void intel_guc_init(struct drm_device *dev)
> > > > struct intel_guc_fw *guc_fw = _priv->guc.guc_fw;
> > > > const char *fw_path;
> > > >  
> > > > +   if (!HAS_GUC(dev)) {
> > > > +   i915.enable_guc_loading = 0;
> > > > +   i915.enable_guc_submission = 0;
> > > > +   fw_path = NULL;
> > > > +   return;
> > > > +   }
> > > 
> > > Instead of this, how about we just patch the code below with:
> > > 
> > > if (!HAS_GUC(dev_priv)) {
> > >   i915.enable_guc_loading = 0;
> > >   i915.enable_guc_submission = 0;
> > > } else {
> > >   /* A negative value means "use platform default" */
> > >   if (i915.enable_guc_loading < 0)
> > >   i915.enable_guc_loading = HAS_GUC_UCODE(dev_priv);
> > >   if (i915.enable_guc_submission < 0)
> > >   i915.enable_guc_submission = HAS_GUC_SCHED(dev_priv);
> > > }
> > 
> > yeap, this works as well. I just went for the simplest option that
> > minimized at most any interactions for platforms where GuC simply
> > doesn't exist.
> > 
> > > 
> > > Or we could even go with our current "design pattern" and create
> > > intel_sanitize_guc_options().
> > 
> > This is indeed a very good idea.
> > 
> > > 
> > > This way we'll be able to avoid adding a second failure code path,
> > > since we already have one for platforms with guc but options disabled.
> > > 
> > > 
> > > > +
> > > > /* A negative value means "use platform default" */
> > > > if (i915.enable_guc_loading < 0)
> > > > i915.enable_guc_loading = HAS_GUC_UCODE(dev);
> > 
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 

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[Intel-gfx] [PATCH] drm/i915/guc: Sanitory checks for platform that dont have GuC

[Anusha Srivatsa]

i915.enable_guc_loading/submission=2 forces the usage of GuC.
For platforms that do not have a GuC, asking the kernel to
use a GuC should not result in an error state. Do extra checks
to see if the platform even has a GuC or not, regardless of the
kernel parameter.

Cc: Zanoni Paulo 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 15 +--
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 7ace96b..15d2d53 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -717,13 +717,16 @@ void intel_guc_init(struct drm_device *dev)
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_guc_fw *guc_fw = _priv->guc.guc_fw;
const char *fw_path;
-
+   if (!HAS_GUC(dev)) {
+   i915.enable_guc_loading = 0;
+   i915.enable_guc_submission = 0;
+   } else {
/* A negative value means "use platform default" */
-   if (i915.enable_guc_loading < 0)
-   i915.enable_guc_loading = HAS_GUC_UCODE(dev);
-   if (i915.enable_guc_submission < 0)
-   i915.enable_guc_submission = HAS_GUC_SCHED(dev);
-
+   if (i915.enable_guc_loading < 0)
+   i915.enable_guc_loading = HAS_GUC_UCODE(dev);
+   if (i915.enable_guc_submission < 0)
+   i915.enable_guc_submission = HAS_GUC_SCHED(dev);
+   }
if (!HAS_GUC_UCODE(dev)) {
fw_path = NULL;
} else if (IS_SKYLAKE(dev)) {
-- 
2.7.4

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Re: [Intel-gfx] [PATCH 5/6] drm/i915/gen9: Get rid of redundant watermark values

[Chris Wilson]

On Wed, Oct 05, 2016 at 06:44:04PM -0300, Paulo Zanoni wrote:
> Em Qua, 2016-10-05 às 11:33 -0400, Lyude escreveu:
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index dd15ae2..c580d3d 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3378,6 +3378,8 @@ static void skylake_update_primary_plane(struct
> > drm_plane *plane,
> >     struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state-
> > >base.crtc);
> >     struct drm_framebuffer *fb = plane_state->base.fb;
> >     const struct skl_wm_values *wm = _priv->wm.skl_results;
> > +   const struct skl_plane_wm *p_wm =
> > +   _state->wm.skl.optimal.planes[0];
> 
> I wish someone would do a patch to convert all these hardcoded values
> to PLANE_X, and convert "int"s  to "enum plane"s everywhere.

Note that this is not PLANE_A, but setting up a shorthand local for

const struct skl_plane_wm *p_wm = crtc_state->wm.skl.optimal.planes;

-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] [PATCH i-g-t 1/2] aubdump: remove already handled -o

[Lionel Landwerlin]

From: Lionel Landwerlin 

Signed-off-by: Lionel Landwerlin 
Cc: Sirisha Gandikota 
---
 tools/intel_aubdump.in | 4 
 1 file changed, 4 deletions(-)

diff --git a/tools/intel_aubdump.in b/tools/intel_aubdump.in
index feee23a..3666b6e 100644
--- a/tools/intel_aubdump.in
+++ b/tools/intel_aubdump.in
@@ -34,10 +34,6 @@ while true; do
  verbose=1
  shift 1
  ;;
- -o*)
- file=${1##-o}
- shift
- ;;
  --output=*)
  file=${1##--output=}
  shift
-- 
2.9.3

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[Intel-gfx] [PATCH v2 i-g-t 2/2] aubdump: add --command option to stream aubdump to another program

[Lionel Landwerlin]

This comes handy if you want to look at your application output without
having to save it into a file. For example, use this with aubinator from
Mesa :

$ intel_aubdump -c '/path/to/aubinator --gen=hsw' my_gl_app

v2: Fix handling empty command line option

Signed-off-by: Lionel Landwerlin 
Cc: Sirisha Gandikota 
---
 tools/aubdump.c| 107 -
 tools/intel_aubdump.in |  31 +-
 2 files changed, 117 insertions(+), 21 deletions(-)

diff --git a/tools/aubdump.c b/tools/aubdump.c
index 30dc742..3b85bc7 100644
--- a/tools/aubdump.c
+++ b/tools/aubdump.c
@@ -50,6 +50,7 @@ static int (*libc_close)(int fd) = close_init_helper;
 static int (*libc_ioctl)(int fd, unsigned long request, ...) = 
ioctl_init_helper;

 static int drm_fd = -1;
+static char *command;
 static char *filename;
 static FILE *file;
 static int gen = 0;
@@ -113,6 +114,82 @@ fail_if(int cond, const char *format, ...)
raise(SIGTRAP);
 }

+static FILE *
+launch_command(void)
+{
+   int i = 0, fds[2];
+   char **args = calloc(strlen(command), sizeof(char *));
+   char *iter = command;
+
+   args[i++] = iter = command;
+
+   while ((iter = strstr(iter, ",")) != NULL) {
+   *iter = '\0';
+   iter += 1;
+   args[i++] = iter;
+   }
+
+   if (pipe(fds) == -1)
+   return NULL;
+
+   switch (fork()) {
+   case 0:
+   dup2(fds[0], 0);
+   fail_if(execv(args[0], args) == -1,
+   "intel_aubdump: fail to launch child command\n");
+   return NULL;
+
+   default:
+   free(args);
+   return fdopen(fds[1], "w");
+
+   case -1:
+   return NULL;
+   }
+}
+
+static void
+maybe_init_output(void)
+{
+   const char *args;
+   static bool initialized = false;
+   int nb_args;
+
+   if (initialized)
+   return;
+
+   args = getenv("INTEL_AUBDUMP_ARGS");
+
+   nb_args = sscanf(args, 
"verbose=%d;file=%m[^;];device=%i;command=%m[^;];",
+, , , );
+   if (nb_args != 4) {
+   if (filename)
+   free(filename);
+   nb_args = sscanf(args, "verbose=%d;file=%m[^;];device=%i;",
+, , );
+   command = strdup("");
+   }
+fail_if(filename == NULL || command == NULL,
+"intel_aubdump: out of memory\n");
+   if (device)
+   device_override = true;
+
+   bos = malloc(MAX_BO_COUNT * sizeof(bos[0]));
+   fail_if(bos == NULL, "intel_aubdump: out of memory\n");
+
+if (strlen(command) != 0) {
+  file = launch_command();
+  fail_if(file == NULL,
+  "intel_aubdump: failed to launch command '%s'\n", command);
+} else {
+  file = fopen(filename, "w+");
+  fail_if(file == NULL,
+  "intel_aubdump: failed to open file '%s'\n", filename);
+}
+
+   initialized = true;
+}
+
 static struct bo *
 get_bo(uint32_t handle)
 {
@@ -140,13 +217,18 @@ align_u64(uint64_t v, uint64_t a)
 static void
 dword_out(uint32_t data)
 {
-   fwrite(, 1, 4, file);
+   fail_if(fwrite(, 1, 4, file) == 0,
+   "Writing to output failed\n");
 }

 static void
 data_out(const void *data, size_t size)
 {
-   fwrite(data, 1, size, file);
+   if (size == 0)
+   return;
+
+   fail_if(fwrite(data, 1, size, file) == 0,
+   "Writing to output failed\n");
 }

 static void
@@ -447,6 +529,8 @@ ioctl(int fd, unsigned long request, ...)
}

if (fd == drm_fd) {
+   maybe_init_output();
+
switch (request) {
case DRM_IOCTL_I915_GETPARAM: {
struct drm_i915_getparam *getparam = argp;
@@ -550,26 +634,8 @@ ioctl(int fd, unsigned long request, ...)
 static void
 init(void)
 {
-   const char *args = getenv("INTEL_AUBDUMP_ARGS");
-
libc_close = dlsym(RTLD_NEXT, "close");
libc_ioctl = dlsym(RTLD_NEXT, "ioctl");
-   fail_if(libc_close == NULL || libc_ioctl == NULL,
-   "intel_aubdump: failed to get libc ioctl or close\n");
-
-   if (sscanf(args, "verbose=%d;file=%m[^;];device=%i",
-  , , ) != 3)
-   filename = strdup("intel.aub");
-   fail_if(filename == NULL, "intel_aubdump: out of memory\n");
-
-   if (device)
-   device_override = true;
-
-   bos = malloc(MAX_BO_COUNT * sizeof(bos[0]));
-   fail_if(bos == NULL, "intel_aubdump: out of memory\n");
-
-   file = fopen(filename, "w+");
-   fail_if(file == NULL, "intel_aubdump: failed to open file '%s'\n", 
filename);
 }

 static int
@@ -596,6 +662,7 @@ ioctl_init_helper(int fd, unsigned long request, ...)
 static void __attribute__ ((destructor))
 fini(void)
 {
+ 

[Intel-gfx] ✗ Fi.CI.BAT: warning for i915/GuC: Make GuC loads default

[Patchwork]

== Series Details ==

Series: i915/GuC: Make GuC loads default
URL   : https://patchwork.freedesktop.org/series/13356/
State : warning

== Summary ==

Series 13356v1 i915/GuC: Make GuC loads default
https://patchwork.freedesktop.org/api/1.0/series/13356/revisions/1/mbox/

Test drv_module_reload_basic:
pass   -> SKIP   (fi-skl-6260u)
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-skl-6770hq)
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-byt-j1900)
Test kms_psr_sink_crc:
Subgroup psr_basic:
pass   -> DMESG-WARN (fi-skl-6700hq)

fi-bdw-5557u total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050 total:244  pass:202  dwarn:0   dfail:0   fail:0   skip:42 
fi-bxt-t5700 total:244  pass:214  dwarn:0   dfail:0   fail:0   skip:30 
fi-byt-j1900 total:244  pass:211  dwarn:1   dfail:0   fail:1   skip:31 
fi-byt-n2820 total:244  pass:208  dwarn:0   dfail:0   fail:1   skip:35 
fi-hsw-4770  total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-hsw-4770r total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ilk-650   total:244  pass:182  dwarn:0   dfail:0   fail:2   skip:60 
fi-ivb-3520m total:244  pass:219  dwarn:0   dfail:0   fail:0   skip:25 
fi-ivb-3770  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 
fi-kbl-7200u total:244  pass:220  dwarn:0   dfail:0   fail:0   skip:24 
fi-skl-6260u total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-skl-6700hqtotal:244  pass:221  dwarn:1   dfail:0   fail:0   skip:22 
fi-skl-6700k total:244  pass:219  dwarn:1   dfail:0   fail:0   skip:24 
fi-skl-6770hqtotal:244  pass:227  dwarn:2   dfail:0   fail:1   skip:14 
fi-snb-2520m total:244  pass:208  dwarn:0   dfail:0   fail:0   skip:36 
fi-snb-2600  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 

Results at /archive/results/CI_IGT_test/Patchwork_2633/

2dff18acaa95a26b882a5f9910d7ded514f18415 drm-intel-nightly: 
2016y-10m-05d-13h-58m-08s UTC integration manifest
dd07634 i915/GuC: Make GuC loads default

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Re: [Intel-gfx] [PATCH 5/6] drm/i915/gen9: Get rid of redundant watermark values

[Paulo Zanoni]

Em Qua, 2016-10-05 às 11:33 -0400, Lyude escreveu:
> Now that we've make skl_wm_levels make a little more sense, we can
> remove all of the redundant wm information. Up until now we'd been
> storing two copies of all of the skl watermarks: one being the
> skl_pipe_wm structs, the other being the global wm struct in
> drm_i915_private containing the raw register values. This is
> confusing
> and problematic, since it means we're prone to accidentally letting
> the
> two copies go out of sync. So, get rid of all of the functions
> responsible for computing the register values and just use a single
> helper, skl_write_wm_level(), to convert and write the new watermarks
> on
> the fly.

I like the direction of this patch too, but there are some small
possible problems. See below.


> 
> Signed-off-by: Lyude 
> Cc: Maarten Lankhorst 
> Cc: Ville Syrjälä 
> Cc: Matt Roper 
> ---
>  drivers/gpu/drm/i915/i915_drv.h  |   2 -
>  drivers/gpu/drm/i915/intel_display.c |  14 ++-
>  drivers/gpu/drm/i915/intel_drv.h |   6 +-
>  drivers/gpu/drm/i915/intel_pm.c  | 203 -
> --
>  drivers/gpu/drm/i915/intel_sprite.c  |   8 +-
>  5 files changed, 88 insertions(+), 145 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 0f97d43..63519ac 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1643,8 +1643,6 @@ struct skl_ddb_allocation {
>  struct skl_wm_values {
>   unsigned dirty_pipes;
>   struct skl_ddb_allocation ddb;
> - uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
> - uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
>  };
>  
>  struct skl_wm_level {
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index dd15ae2..c580d3d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3378,6 +3378,8 @@ static void skylake_update_primary_plane(struct
> drm_plane *plane,
>   struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state-
> >base.crtc);
>   struct drm_framebuffer *fb = plane_state->base.fb;
>   const struct skl_wm_values *wm = _priv->wm.skl_results;
> + const struct skl_plane_wm *p_wm =
> + _state->wm.skl.optimal.planes[0];

I wish someone would do a patch to convert all these hardcoded values
to PLANE_X, and convert "int"s  to "enum plane"s everywhere.


>   int pipe = intel_crtc->pipe;
>   u32 plane_ctl;
>   unsigned int rotation = plane_state->base.rotation;
> @@ -3414,7 +3416,7 @@ static void skylake_update_primary_plane(struct
> drm_plane *plane,
>   intel_crtc->adjusted_y = src_y;
>  
>   if (wm->dirty_pipes & drm_crtc_mask(_crtc->base))
> - skl_write_plane_wm(intel_crtc, wm, 0);
> + skl_write_plane_wm(intel_crtc, p_wm, >ddb, 0);
>  
>   I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
>   I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
> @@ -3448,6 +3450,8 @@ static void
> skylake_disable_primary_plane(struct drm_plane *primary,
>   struct drm_device *dev = crtc->dev;
>   struct drm_i915_private *dev_priv = to_i915(dev);
>   struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> + struct intel_crtc_state *cstate = to_intel_crtc_state(crtc-
> >state);
> + const struct skl_plane_wm *p_wm = 
> >wm.skl.optimal.planes[0];
>   int pipe = intel_crtc->pipe;
>  
>   /*
> @@ -3455,7 +3459,8 @@ static void
> skylake_disable_primary_plane(struct drm_plane *primary,
>    * plane's visiblity isn't actually changing neither is its
> watermarks.
>    */
>   if (!crtc->primary->state->visible)
> - skl_write_plane_wm(intel_crtc, _priv-
> >wm.skl_results, 0);
> + skl_write_plane_wm(intel_crtc, p_wm,
> +    _priv->wm.skl_results.ddb,
> 0);
>  
>   I915_WRITE(PLANE_CTL(pipe, 0), 0);
>   I915_WRITE(PLANE_SURF(pipe, 0), 0);
> @@ -10819,12 +10824,15 @@ static void i9xx_update_cursor(struct
> drm_crtc *crtc, u32 base,
>   struct drm_device *dev = crtc->dev;
>   struct drm_i915_private *dev_priv = to_i915(dev);
>   struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> + struct intel_crtc_state *cstate = to_intel_crtc_state(crtc-
> >state);
>   const struct skl_wm_values *wm = _priv->wm.skl_results;
> + const struct skl_plane_wm *p_wm =
> + >wm.skl.optimal.planes[PLANE_CURSOR];
>   int pipe = intel_crtc->pipe;
>   uint32_t cntl = 0;
>  
>   if (INTEL_GEN(dev_priv) >= 9 && wm->dirty_pipes &
> drm_crtc_mask(crtc))
> - skl_write_cursor_wm(intel_crtc, wm);
> + skl_write_cursor_wm(intel_crtc, p_wm, >ddb);
>  
>   if (plane_state && plane_state->base.visible) {
>   cntl = MCURSOR_GAMMA_ENABLE;
> diff --git 

[Intel-gfx] [PATCH] i915/GuC: Make GuC loads default

[Anusha Srivatsa]

Proper functioning of HuC requires GuC to be
loaded. Make GuC loads default so that HuC works
seemlessly.
Also, note that GuC submission is not made default
and still needs to be given as a kernel parameter.
Once the issues around GuC submission is resolved it
is intended to make it default as well.

It is now safe to make GuC loads default.

Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/i915_params.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 768ad89..256a512 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -55,7 +55,7 @@ struct i915_params i915 __read_mostly = {
.verbose_state_checks = 1,
.nuclear_pageflip = 0,
.edp_vswing = 0,
-   .enable_guc_loading = 0,
+   .enable_guc_loading = -1,
.enable_guc_submission = 0,
.guc_log_level = -1,
.enable_dp_mst = true,
@@ -209,7 +209,7 @@ MODULE_PARM_DESC(edp_vswing,
 module_param_named_unsafe(enable_guc_loading, i915.enable_guc_loading, int, 
0400);
 MODULE_PARM_DESC(enable_guc_loading,
"Enable GuC firmware loading "
-   "(-1=auto, 0=never [default], 1=if available, 2=required)");
+   "(-1=auto [default], 0=never, 1=if available, 2=required )");
 
 module_param_named_unsafe(enable_guc_submission, i915.enable_guc_submission, 
int, 0400);
 MODULE_PARM_DESC(enable_guc_submission,
-- 
2.7.4

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[Intel-gfx] [PATCH v2 1/2] drm/i915: Reduce trickery in DEV_INFO_FOR_EACH_FLAG

[Joonas Lahtinen]

Get rid of SEP_SEMICOLON and SEP_BLANK in DEV_INFO_FOR_EACH_FLAG.
Consolidate the debug output so that instead of one huge line with
"cap1,cap2,capN" each capability is split to own line and displayed
as "capN: [yes|no]" to make the dumps more historically informative.

v2:
- Do not break auto-indent by keeping semicolon after macro (Jani)
- Consolidate and use yesno() in all locations (Chris)

Cc: Jani Nikula 
Cc: Chris Wilson 
Reviewed-by: Chris Wilson 
Signed-off-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  4 +-
 drivers/gpu/drm/i915/i915_drv.h  | 98 +++-
 drivers/gpu/drm/i915/i915_gpu_error.c|  4 +-
 drivers/gpu/drm/i915/intel_device_info.c | 16 ++
 4 files changed, 54 insertions(+), 68 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 4fb9d82..924013b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -69,10 +69,8 @@ static int i915_capabilities(struct seq_file *m, void *data)
seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
-#define SEP_SEMICOLON ;
-   DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
+   DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
 #undef PRINT_FLAG
-#undef SEP_SEMICOLON
 
return 0;
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 91ff3d7..8b0500f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -634,55 +634,52 @@ struct intel_csr {
uint32_t allowed_dc_mask;
 };
 
-#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
-   func(is_mobile) sep \
-   func(is_i85x) sep \
-   func(is_i915g) sep \
-   func(is_i945gm) sep \
-   func(is_g33) sep \
-   func(hws_needs_physical) sep \
-   func(is_g4x) sep \
-   func(is_pineview) sep \
-   func(is_broadwater) sep \
-   func(is_crestline) sep \
-   func(is_ivybridge) sep \
-   func(is_valleyview) sep \
-   func(is_cherryview) sep \
-   func(is_haswell) sep \
-   func(is_broadwell) sep \
-   func(is_skylake) sep \
-   func(is_broxton) sep \
-   func(is_kabylake) sep \
-   func(is_preliminary) sep \
-   func(has_fbc) sep \
-   func(has_psr) sep \
-   func(has_runtime_pm) sep \
-   func(has_csr) sep \
-   func(has_resource_streamer) sep \
-   func(has_rc6) sep \
-   func(has_rc6p) sep \
-   func(has_dp_mst) sep \
-   func(has_gmbus_irq) sep \
-   func(has_hw_contexts) sep \
-   func(has_logical_ring_contexts) sep \
-   func(has_l3_dpf) sep \
-   func(has_gmch_display) sep \
-   func(has_guc) sep \
-   func(has_pipe_cxsr) sep \
-   func(has_hotplug) sep \
-   func(cursor_needs_physical) sep \
-   func(has_overlay) sep \
-   func(overlay_needs_physical) sep \
-   func(supports_tv) sep \
-   func(has_llc) sep \
-   func(has_snoop) sep \
-   func(has_ddi) sep \
-   func(has_fpga_dbg) sep \
+#define DEV_INFO_FOR_EACH_FLAG(func) \
+   func(is_mobile); \
+   func(is_i85x); \
+   func(is_i915g); \
+   func(is_i945gm); \
+   func(is_g33); \
+   func(hws_needs_physical); \
+   func(is_g4x); \
+   func(is_pineview); \
+   func(is_broadwater); \
+   func(is_crestline); \
+   func(is_ivybridge); \
+   func(is_valleyview); \
+   func(is_cherryview); \
+   func(is_haswell); \
+   func(is_broadwell); \
+   func(is_skylake); \
+   func(is_broxton); \
+   func(is_kabylake); \
+   func(is_preliminary); \
+   func(has_fbc); \
+   func(has_psr); \
+   func(has_runtime_pm); \
+   func(has_csr); \
+   func(has_resource_streamer); \
+   func(has_rc6); \
+   func(has_rc6p); \
+   func(has_dp_mst); \
+   func(has_gmbus_irq); \
+   func(has_hw_contexts); \
+   func(has_logical_ring_contexts); \
+   func(has_l3_dpf); \
+   func(has_gmch_display); \
+   func(has_guc); \
+   func(has_pipe_cxsr); \
+   func(has_hotplug); \
+   func(cursor_needs_physical); \
+   func(has_overlay); \
+   func(overlay_needs_physical); \
+   func(supports_tv); \
+   func(has_llc); \
+   func(has_snoop); \
+   func(has_ddi); \
+   func(has_fpga_dbg); \
func(has_pooled_eu)
 
-#define DEFINE_FLAG(name) u8 name:1
-#define SEP_SEMICOLON ;
-
 struct sseu_dev_info {
u8 slice_mask;
u8 subslice_mask;
@@ -710,7 +707,9 @@ struct intel_device_info {
u16 gen_mask;
u8 ring_mask; /* Rings supported by the HW */
u8 num_rings;
-   DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
+#define DEFINE_FLAG(name) u8 name:1
+   

[Intel-gfx] [PATCH v2 2/2] drm/i915: Sort DEV_INFO_FOR_EACH_FLAG

[Joonas Lahtinen]

Sort DEV_INFO_FOR_EACH_FLAG to alphabetical order (except is_*).

v2:
- Add comments in the hope of maintaining order (Chris)

Cc: Chris Wilson 
Reviewed-by: Chris Wilson 
Signed-off-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_drv.h | 38 --
 1 file changed, 20 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8b0500f..414568a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -635,12 +635,12 @@ struct intel_csr {
 };
 
 #define DEV_INFO_FOR_EACH_FLAG(func) \
+   /* Keep is_* in chronological order */ \
func(is_mobile); \
func(is_i85x); \
func(is_i915g); \
func(is_i945gm); \
func(is_g33); \
-   func(hws_needs_physical); \
func(is_g4x); \
func(is_pineview); \
func(is_broadwater); \
@@ -654,31 +654,33 @@ struct intel_csr {
func(is_broxton); \
func(is_kabylake); \
func(is_preliminary); \
-   func(has_fbc); \
-   func(has_psr); \
-   func(has_runtime_pm); \
+   /* Keep has_* in alphabetical order */ \
func(has_csr); \
-   func(has_resource_streamer); \
-   func(has_rc6); \
-   func(has_rc6p); \
+   func(has_ddi); \
func(has_dp_mst); \
+   func(has_fbc); \
+   func(has_fpga_dbg); \
func(has_gmbus_irq); \
-   func(has_hw_contexts); \
-   func(has_logical_ring_contexts); \
-   func(has_l3_dpf); \
func(has_gmch_display); \
func(has_guc); \
-   func(has_pipe_cxsr); \
func(has_hotplug); \
-   func(cursor_needs_physical); \
-   func(has_overlay); \
-   func(overlay_needs_physical); \
-   func(supports_tv); \
+   func(has_hw_contexts); \
+   func(has_l3_dpf); \
func(has_llc); \
+   func(has_logical_ring_contexts); \
+   func(has_overlay); \
+   func(has_pipe_cxsr); \
+   func(has_pooled_eu); \
+   func(has_psr); \
+   func(has_rc6); \
+   func(has_rc6p); \
+   func(has_resource_streamer); \
+   func(has_runtime_pm); \
func(has_snoop); \
-   func(has_ddi); \
-   func(has_fpga_dbg); \
-   func(has_pooled_eu)
+   func(cursor_needs_physical); \
+   func(hws_needs_physical); \
+   func(overlay_needs_physical); \
+   func(supports_tv)
 
 struct sseu_dev_info {
u8 slice_mask;
-- 
2.7.4

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[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [v2,1/2] drm/i915: Reduce trickery in DEV_INFO_FOR_EACH_FLAG

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/2] drm/i915: Reduce trickery in 
DEV_INFO_FOR_EACH_FLAG
URL   : https://patchwork.freedesktop.org/series/13319/
State : warning

== Summary ==

Series 13319v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/13319/revisions/1/mbox/

Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-a:
pass   -> DMESG-WARN (fi-skl-6700k)
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-byt-j1900)

fi-bdw-5557u total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050 total:244  pass:202  dwarn:0   dfail:0   fail:0   skip:42 
fi-bxt-t5700 total:244  pass:214  dwarn:0   dfail:0   fail:0   skip:30 
fi-byt-j1900 total:244  pass:210  dwarn:2   dfail:0   fail:1   skip:31 
fi-byt-n2820 total:244  pass:208  dwarn:0   dfail:0   fail:1   skip:35 
fi-hsw-4770  total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-hsw-4770r total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ilk-650   total:244  pass:182  dwarn:0   dfail:0   fail:2   skip:60 
fi-ivb-3520m total:244  pass:219  dwarn:0   dfail:0   fail:0   skip:25 
fi-ivb-3770  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 
fi-skl-6260u total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hqtotal:244  pass:221  dwarn:1   dfail:0   fail:0   skip:22 
fi-skl-6700k total:244  pass:218  dwarn:2   dfail:0   fail:0   skip:24 
fi-skl-6770hqtotal:244  pass:228  dwarn:1   dfail:0   fail:1   skip:14 
fi-snb-2520m total:244  pass:208  dwarn:0   dfail:0   fail:0   skip:36 
fi-snb-2600  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 

Results at /archive/results/CI_IGT_test/Patchwork_2627/

0ff41ae4e5f083e3abcc170c1dab648f28b3 drm-intel-nightly: 
2016y-10m-05d-09h-47m-15s UTC integration manifest
a43cca5 drm/i915: Sort DEV_INFO_FOR_EACH_FLAG
caa639e drm/i915: Reduce trickery in DEV_INFO_FOR_EACH_FLAG

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[Intel-gfx] [PATCH 9/9] drm/i915: Address broxton phy registers based on phy and channel number

[Ander Conselvan de Oliveira]

The port registers related to the phys in broxton map to different
channels and specific phys. Make that mapping explicit.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/i915_drv.h   |   2 +
 drivers/gpu/drm/i915/i915_reg.h   | 211 +-
 drivers/gpu/drm/i915/intel_dpio_phy.c | 131 +++--
 drivers/gpu/drm/i915/intel_dpll_mgr.c |  84 --
 4 files changed, 222 insertions(+), 206 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 77f1374..c3fa29a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3735,6 +3735,8 @@ u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, 
u32 reg);
 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
 
 /* intel_dpio_phy.c */
+void bxt_port_to_phy_channel(enum port port,
+u32 *phy, enum dpio_channel *ch);
 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
  enum port port, u32 margin, u32 scale,
  u32 enable, u32 deemphasis);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d3802c6..416cbb1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1187,6 +1187,9 @@ enum skl_disp_power_wells {
 #define   DPIO_UPAR_SHIFT  30
 
 /* BXT PHY registers */
+#define BXT_PHY1_BASE  0x162000
+#define BXT_PHY0_BASE  0x6C000
+
 #define _BXT_PHY(phy, a, b)_MMIO_PIPE((phy), (a), (b))
 
 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
@@ -1216,31 +1219,26 @@ enum skl_disp_power_wells {
 #define   PORT_PLL_REF_SEL (1 << 27)
 #define BXT_PORT_PLL_ENABLE(port)  _MMIO_PORT(port, _PORT_PLL_A, 
_PORT_PLL_B)
 
-#define _PORT_PLL_EBB_0_A  0x162034
-#define _PORT_PLL_EBB_0_B  0x6C034
-#define _PORT_PLL_EBB_0_C  0x6C340
+#define _PORT_PLL_EBB_0_CH00x34
+#define _PORT_PLL_EBB_0_CH10x340
 #define   PORT_PLL_P1_SHIFT13
 #define   PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT)
 #define   PORT_PLL_P1(x)   ((x)  << PORT_PLL_P1_SHIFT)
 #define   PORT_PLL_P2_SHIFT8
 #define   PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT)
 #define   PORT_PLL_P2(x)   ((x)  << PORT_PLL_P2_SHIFT)
-#define BXT_PORT_PLL_EBB_0(port)   _MMIO_PORT3(port, _PORT_PLL_EBB_0_A, \
-   _PORT_PLL_EBB_0_B,  \
-   _PORT_PLL_EBB_0_C)
+#define BXT_PORT_PLL_EBB_0(base, ch)   \
+   _MMIO((base) + _PIPE((ch), _PORT_PLL_EBB_0_CH0, _PORT_PLL_EBB_0_CH1))
 
-#define _PORT_PLL_EBB_4_A  0x162038
-#define _PORT_PLL_EBB_4_B  0x6C038
-#define _PORT_PLL_EBB_4_C  0x6C344
+#define _PORT_PLL_EBB_4_CH00x38
+#define _PORT_PLL_EBB_4_CH10x344
 #define   PORT_PLL_10BIT_CLK_ENABLE(1 << 13)
 #define   PORT_PLL_RECALIBRATE (1 << 14)
-#define BXT_PORT_PLL_EBB_4(port)   _MMIO_PORT3(port, _PORT_PLL_EBB_4_A, \
-   _PORT_PLL_EBB_4_B,  \
-   _PORT_PLL_EBB_4_C)
+#define BXT_PORT_PLL_EBB_4(base, ch)   \
+   _MMIO((base) + _PIPE((ch), _PORT_PLL_EBB_4_CH0, _PORT_PLL_EBB_4_CH1))
 
-#define _PORT_PLL_0_A  0x162100
-#define _PORT_PLL_0_B  0x6C100
-#define _PORT_PLL_0_C  0x6C380
+#define _PORT_PLL_0_CH00x100
+#define _PORT_PLL_0_CH10x380
 /* PORT_PLL_0_A */
 #define   PORT_PLL_M2_MASK 0xFF
 /* PORT_PLL_1_A */
@@ -1267,65 +1265,43 @@ enum skl_disp_power_wells {
 #define  PORT_PLL_DCO_AMP_DEFAULT  15
 #define  PORT_PLL_DCO_AMP_MASK 0x3c00
 #define  PORT_PLL_DCO_AMP(x)   ((x)<<10)
-#define _PORT_PLL_BASE(port)   _PORT3(port, _PORT_PLL_0_A, \
-   _PORT_PLL_0_B,  \
-   _PORT_PLL_0_C)
-#define BXT_PORT_PLL(port, idx)_MMIO(_PORT_PLL_BASE(port) + 
(idx) * 4)
+#define _PORT_PLL_BASE(base, ch)   \
+   ((base) + _PIPE((ch), _PORT_PLL_0_CH0, _PORT_PLL_0_CH1))
+#define BXT_PORT_PLL(base, ch, idx)\
+   _MMIO(_PORT_PLL_BASE(base, ch) + (idx) * 4)
 
 /* BXT PHY common lane registers */
-#define _PORT_CL1CM_DW0_A  0x162000
-#define _PORT_CL1CM_DW0_BC 0x6C000
+#define BXT_PORT_CL1CM_DW0(base)   _MMIO((base) + 0x0)
 #define   PHY_POWER_GOOD   (1 << 16)
 #define   PHY_RESERVED (1 << 7)
-#define BXT_PORT_CL1CM_DW0(phy)_BXT_PHY((phy), 
_PORT_CL1CM_DW0_BC, \
-

[Intel-gfx] [PATCH 6/9] drm/i915: Move broxton vswing sequence to intel_dpio_phy.c

[Ander Conselvan de Oliveira]

The vswing sequence is related to the DPIO phy, so move it closer to the
rest of DPIO phy related code.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/i915_drv.h   |  3 +++
 drivers/gpu/drm/i915/intel_ddi.c  | 38 +-
 drivers/gpu/drm/i915/intel_dpio_phy.c | 39 +++
 3 files changed, 47 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8bdbbb5..77f1374 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3735,6 +3735,9 @@ u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, 
u32 reg);
 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
 
 /* intel_dpio_phy.c */
+void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
+ enum port port, u32 margin, u32 scale,
+ u32 enable, u32 deemphasis);
 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index d69d231..f27cd67 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1477,7 +1477,6 @@ static void bxt_ddi_vswing_sequence(struct 
drm_i915_private *dev_priv,
 {
const struct bxt_ddi_buf_trans *ddi_translations;
u32 n_entries, i;
-   uint32_t val;
 
if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
@@ -1506,38 +1505,11 @@ static void bxt_ddi_vswing_sequence(struct 
drm_i915_private *dev_priv,
}
}
 
-   /*
-* While we write to the group register to program all lanes at once we
-* can read only lane registers and we pick lanes 0/1 for that.
-*/
-   val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
-   val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
-   I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
-
-   val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
-   val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
-   val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
-  ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
-   I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
-
-   val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
-   val &= ~SCALE_DCOMP_METHOD;
-   if (ddi_translations[level].enable)
-   val |= SCALE_DCOMP_METHOD;
-
-   if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
-   DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
-
-   I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
-
-   val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
-   val &= ~DE_EMPHASIS;
-   val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
-   I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
-
-   val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
-   val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
-   I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
+   bxt_ddi_phy_set_signal_level(dev_priv, port,
+ddi_translations[level].margin,
+ddi_translations[level].scale,
+ddi_translations[level].enable,
+ddi_translations[level].deemphasis);
 }
 
 static uint32_t translate_signal_level(int signal_levels)
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c 
b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 6806296..2a18724 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -114,6 +114,45 @@
  * -
  */
 
+void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
+ enum port port, u32 margin, u32 scale,
+ u32 enable, u32 deemphasis)
+{
+   u32 val;
+
+   /*
+* While we write to the group register to program all lanes at once we
+* can read only lane registers and we pick lanes 0/1 for that.
+*/
+   val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
+   val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
+   I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
+
+   val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
+   val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
+   val |= margin << MARGIN_000_SHIFT | scale << UNIQ_TRANS_SCALE_SHIFT;
+   I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
+
+   val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
+   val &= ~SCALE_DCOMP_METHOD;
+   if (enable)
+   val |= SCALE_DCOMP_METHOD;
+
+   if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & 

[Intel-gfx] [PATCH 4/9] drm/i915: Move broxton phy code to intel_dpio_phy.c

[Ander Conselvan de Oliveira]

The phy in broxton is also a dpio phy, similar to cherryview but with
programming through MMIO. So move the code together with the other
similar phys.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/i915_drv.h   |  12 ++
 drivers/gpu/drm/i915/intel_ddi.c  | 322 +
 drivers/gpu/drm/i915/intel_dpio_phy.c | 327 ++
 drivers/gpu/drm/i915/intel_drv.h  |   6 -
 4 files changed, 341 insertions(+), 326 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 93c90b9..8bdbbb5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3735,6 +3735,18 @@ u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, 
u32 reg);
 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
 
 /* intel_dpio_phy.c */
+void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
+void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
+bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
+   enum dpio_phy phy);
+bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
+ enum dpio_phy phy);
+uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
+uint8_t lane_count);
+void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
+uint8_t lane_lat_optim_mask);
+uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
+
 void chv_set_phy_signal_level(struct intel_encoder *encoder,
  u32 deemph_reg_value, u32 margin_reg_value,
  bool uniq_trans_scale);
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 1dc7543..d69d231 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1853,332 +1853,14 @@ static void intel_disable_ddi(struct intel_encoder 
*intel_encoder,
}
 }
 
-bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
-   enum dpio_phy phy)
-{
-   enum port port;
-
-   if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
-   return false;
-
-   if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
-(PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
-   DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't 
settled\n",
-phy);
-
-   return false;
-   }
-
-   if (phy == DPIO_PHY1 &&
-   !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE)) {
-   DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't done\n");
-
-   return false;
-   }
-
-   if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
-   DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n",
-phy);
-
-   return false;
-   }
-
-   for_each_port_masked(port,
-phy == DPIO_PHY0 ? BIT(PORT_B) | BIT(PORT_C) :
-   BIT(PORT_A)) {
-   u32 tmp = I915_READ(BXT_PHY_CTL(port));
-
-   if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
-   DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane "
-"for port %c powered down "
-"(PHY_CTL %08x)\n",
-phy, port_name(port), tmp);
-
-   return false;
-   }
-   }
-
-   return true;
-}
-
-static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
-{
-   u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
-
-   return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
-}
-
-static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
- enum dpio_phy phy)
-{
-   if (intel_wait_for_register(dev_priv,
-   BXT_PORT_REF_DW3(phy),
-   GRC_DONE, GRC_DONE,
-   10))
-   DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
-}
-
-void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
-{
-   u32 val;
-
-   if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
-   /* Still read out the GRC value for state verification */
-   if (phy == DPIO_PHY0)
-   dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
-
-   if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
-   DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
-"won't reprogram it\n", phy);
-
-   return;
- 

[Intel-gfx] [PATCH 1/9] drm/i915: Rename struct i915_power_well field data to id

[Ander Conselvan de Oliveira]

Calling it data seems to imply arbitrary data can be associated with the
power well. However, that field is used for look ups and expected to be
unique, so rename it.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/i915_drv.h |   3 +-
 drivers/gpu/drm/i915/intel_runtime_pm.c | 112 
 2 files changed, 58 insertions(+), 57 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4613f03..5bd3f59 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1316,7 +1316,8 @@ struct i915_power_well {
/* cached hw enabled state */
bool hw_enabled;
unsigned long domains;
-   unsigned long data;
+   /* unique identifier for this power well */
+   unsigned long id;
const struct i915_power_well_ops *ops;
 };
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6c11168..4ecaf6a 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -331,7 +331,7 @@ static void skl_power_well_post_enable(struct 
drm_i915_private *dev_priv,
 * sure vgacon can keep working normally without triggering interrupts
 * and error messages.
 */
-   if (power_well->data == SKL_DISP_PW_2) {
+   if (power_well->id == SKL_DISP_PW_2) {
vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
vga_put(pdev, VGA_RSRC_LEGACY_IO);
@@ -344,7 +344,7 @@ static void skl_power_well_post_enable(struct 
drm_i915_private *dev_priv,
 static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
   struct i915_power_well *power_well)
 {
-   if (power_well->data == SKL_DISP_PW_2)
+   if (power_well->id == SKL_DISP_PW_2)
gen8_irq_power_well_pre_disable(dev_priv,
1 << PIPE_C | 1 << PIPE_B);
 }
@@ -659,7 +659,7 @@ static void
 gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv,
  struct i915_power_well *power_well)
 {
-   enum skl_disp_power_wells power_well_id = power_well->data;
+   enum skl_disp_power_wells power_well_id = power_well->id;
u32 val;
u32 mask;
 
@@ -704,7 +704,7 @@ static void skl_set_power_well(struct drm_i915_private 
*dev_priv,
tmp = I915_READ(HSW_PWR_WELL_DRIVER);
fuse_status = I915_READ(SKL_FUSE_STATUS);
 
-   switch (power_well->data) {
+   switch (power_well->id) {
case SKL_DISP_PW_1:
if (intel_wait_for_register(dev_priv,
SKL_FUSE_STATUS,
@@ -728,13 +728,13 @@ static void skl_set_power_well(struct drm_i915_private 
*dev_priv,
case SKL_DISP_PW_MISC_IO:
break;
default:
-   WARN(1, "Unknown power well %lu\n", power_well->data);
+   WARN(1, "Unknown power well %lu\n", power_well->id);
return;
}
 
-   req_mask = SKL_POWER_WELL_REQ(power_well->data);
+   req_mask = SKL_POWER_WELL_REQ(power_well->id);
enable_requested = tmp & req_mask;
-   state_mask = SKL_POWER_WELL_STATE(power_well->data);
+   state_mask = SKL_POWER_WELL_STATE(power_well->id);
is_enabled = tmp & state_mask;
 
if (!enable && enable_requested)
@@ -770,14 +770,14 @@ static void skl_set_power_well(struct drm_i915_private 
*dev_priv,
  power_well->name, enable ? "enable" : "disable");
 
if (check_fuse_status) {
-   if (power_well->data == SKL_DISP_PW_1) {
+   if (power_well->id == SKL_DISP_PW_1) {
if (intel_wait_for_register(dev_priv,
SKL_FUSE_STATUS,
SKL_FUSE_PG1_DIST_STATUS,
SKL_FUSE_PG1_DIST_STATUS,
1))
DRM_ERROR("PG1 distributing status timeout\n");
-   } else if (power_well->data == SKL_DISP_PW_2) {
+   } else if (power_well->id == SKL_DISP_PW_2) {
if (intel_wait_for_register(dev_priv,
SKL_FUSE_STATUS,
SKL_FUSE_PG2_DIST_STATUS,
@@ -819,8 +819,8 @@ static void hsw_power_well_disable(struct drm_i915_private 
*dev_priv,
 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
 {
-   uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
-   SKL_POWER_WELL_STATE(power_well->data);
+   uint32_t mask 

[Intel-gfx] [PATCH 3/9] drm/i915: Pass lane count to bxt_ddi_phy_calc_lane_optmin_mask()

[Ander Conselvan de Oliveira]

Pass lane count to bxt_ddi_phy_calc_lane_optmin_mask() instead of having
it extract that number from a pipe_config to decouple the phy code from
intel_crtc_state.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/intel_ddi.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 35f0b7c..1dc7543 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2120,9 +2120,9 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private 
*dev_priv,
 
 static uint8_t
 bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
-struct intel_crtc_state *pipe_config)
+uint8_t lane_count)
 {
-   switch (pipe_config->lane_count) {
+   switch (lane_count) {
case 1:
return 0;
case 2:
@@ -2130,7 +2130,7 @@ bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder 
*encoder,
case 4:
return BIT(3) | BIT(2) | BIT(0);
default:
-   MISSING_CASE(pipe_config->lane_count);
+   MISSING_CASE(lane_count);
 
return 0;
}
@@ -2347,7 +2347,7 @@ static bool intel_ddi_compute_config(struct intel_encoder 
*encoder,
if (IS_BROXTON(dev_priv) && ret)
pipe_config->lane_lat_optim_mask =
bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
-pipe_config);
+
pipe_config->lane_count);
 
return ret;
 
-- 
2.5.5

___
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[Intel-gfx] [PULL] topic/drm-misc

[Daniel Vetter]

Hi Dave,

Another attempt, this time rebased and without the pipe crc patches:
- display_info cleanups from Ville
- make prime/gem lookups faster with rbtrees (Chris)
- misc stuff all over

Cheers, Daniel


The following changes since commit c2cbc38b9715bd8318062e600668fc30e5a3fbfa:

  drm: virtio: reinstate drm_virtio_set_busid() (2016-10-04 13:10:30 +1000)

are available in the git repository at:

  git://anongit.freedesktop.org/drm-intel tags/topic/drm-misc-2016-10-05

for you to fetch changes up to 0546d685f07cc4fc5748fd36e57d167877c2842d:

  drm/rockchip: analogix_dp: Refuse to enable PSR if panel doesn't support it 
(2016-10-04 08:23:17 +0200)


Baoyou Xie (3):
  drm/rockchip: add missing header dependencies
  drm/rockchip: mark symbols static where possible
  drm/mediatek: mark symbols static where possible

Chris Wilson (1):
  drm: Convert prime dma-buf <-> handle to rbtree

Daniel Vetter (1):
  drm: Document caveats around atomic event handling

Emilio López (1):
  uapi: add missing install of sync_file.h

Joe Perches (1):
  drm: Simplify drm_printk to reduce object size quite a bit

Stefan Christ (1):
  drm/fb-helper: add DRM_FB_HELPER_DEFAULT_OPS for fb_ops

Tomeu Vizoso (2):
  drm/bridge: analogix_dp: Add analogix_dp_psr_supported
  drm/rockchip: analogix_dp: Refuse to enable PSR if panel doesn't support 
it

Ville Syrjälä (10):
  drm/edid: Clear old audio latency values before parsing the new EDID
  drm/edid: Clear old dvi_dual/max_tmds_clock before parsing the new EDID
  drm/edid: Make max_tmds_clock kHz instead of MHz
  drm/edid: Move dvi_dual/max_tmds_clock to drm_display_info
  drm/edid: Don't pass around drm_display_info needlessly
  drm/edid: Reduce the number of times we parse the CEA extension block
  drm/edid: Clear the old cea_rev when there's no CEA extension in the new 
EDID
  drm/edid: Move dvi_dual/max_tmds_clock parsing out from drm_edid_to_eld()
  drm/i915: Replace a bunch of connector->base.display_info with a local 
variable
  drm/i915: Account for sink max TMDS clock when checking the port clock

 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c |   4 +-
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c |   8 +
 drivers/gpu/drm/drm_drv.c  |   5 +-
 drivers/gpu/drm/drm_edid.c | 248 +++--
 drivers/gpu/drm/drm_irq.c  |  32 ++-
 drivers/gpu/drm/drm_prime.c|  85 ++-
 drivers/gpu/drm/i915/intel_display.c   |  14 +-
 drivers/gpu/drm/i915/intel_hdmi.c  |   9 +-
 drivers/gpu/drm/mediatek/mtk_hdmi.c|  11 +-
 drivers/gpu/drm/radeon/radeon_connectors.c |   4 +-
 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c|   3 +
 drivers/gpu/drm/rockchip/rockchip_drm_drv.c|   4 +-
 drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c  |   1 +
 include/drm/bridge/analogix_dp.h   |   1 +
 include/drm/drmP.h |  35 ++-
 include/drm/drm_connector.h|  15 +-
 include/drm/drm_crtc.h |  56 +++--
 include/drm/drm_fb_helper.h|  13 ++
 include/uapi/linux/Kbuild  |   1 +
 19 files changed, 361 insertions(+), 188 deletions(-)

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH igt 2/2] tests/gem_exec_suspend: Add basic s4-devices subtest

[Imre Deak]

On ke, 2016-10-05 at 10:22 +0100, Chris Wilson wrote:
> On Wed, Oct 05, 2016 at 12:04:53PM +0300, Imre Deak wrote:
> > Add a new subtest that performs suspend-to-disk, but instead of
> > doing
> > the full sequence it suspends/resumes only devices. A failed s4
> > subtest
> > and a successful s4-devices subtest would indicate a kernel core or
> > BIOS
> > problem as opposed to some issue in the driver.
> 
> Worth doing for suspend as well? Same argument for easier diagnosis
> of
> any problem.

Yes, can add that. Btw, these pm_test cycles complete faster (for
instance 7 sec for s3-devices vs. 20 sec s3).

> > Signed-off-by: Imre Deak 
> 
> Looks sensible to me.
> -Chris
> 
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Move long hpd handling into the hotplug work

[Ville Syrjälä]

On Mon, Oct 03, 2016 at 02:39:16PM +0300, Ander Conselvan De Oliveira wrote:
> On Mon, 2016-10-03 at 10:55 +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä 
> > 
> > We can't rely on connector->status in the detect() hook if the long hpd
> > was already handled by the dig_port_work as that won't update
> > connector->status. Thus we have to defer the long hpd handling entirely
> > until the hotplug work runs to avoid the double long hpd handling
> > the "detect_done" flag is trying to prevent.
> 
> This is better indeed. But perhaps add a note here about the next patch, since
> this one doesn't actually change the use of connector->status usage in 
> detect().
> 
> For both patches:
> 
> Reviewed-by: Ander Conselvan de Oliveira 

Thanks. I added a small note to 1/2 and pushed both patches to dinq.

> 
> > 
> > Cc: Damien Cassou 
> > Cc: freedesktop@gp.mailgun.org
> > Cc: Arno 
> > Cc: Shubhangi Shrivastava 
> > Cc: Sivakumar Thulasimani 
> > Cc: Ander Conselvan de Oliveira 
> > Cc: sta...@vger.kernel.org
> > Tested-by: Arno 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83348
> > Signed-off-by: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 48 --
> > ---
> >  1 file changed, 23 insertions(+), 25 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 9448d898d80b..96caa469e3a8 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -4827,36 +4827,34 @@ intel_dp_hpd_pulse(struct intel_digital_port
> > *intel_dig_port, bool long_hpd)
> >       port_name(intel_dig_port->port),
> >       long_hpd ? "long" : "short");
> >  
> > +   if (long_hpd) {
> > +   intel_dp->detect_done = false;
> > +   return IRQ_NONE;
> > +   }
> > +
> >     power_domain = intel_display_port_aux_power_domain(intel_encoder);
> >     intel_display_power_get(dev_priv, power_domain);
> >  
> > -   if (long_hpd) {
> > -   intel_dp_long_pulse(intel_dp->attached_connector);
> > -   if (intel_dp->is_mst)
> > -   ret = IRQ_HANDLED;
> > -   goto put_power;
> > -
> > -   } else {
> > -   if (intel_dp->is_mst) {
> > -   if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
> > -   /*
> > -    * If we were in MST mode, and device is not
> > -    * there, get out of MST mode
> > -    */
> > -   DRM_DEBUG_KMS("MST device may have
> > disappeared %d vs %d\n",
> > -     intel_dp->is_mst, intel_dp-
> > >mst_mgr.mst_state);
> > -   intel_dp->is_mst = false;
> > -   drm_dp_mst_topology_mgr_set_mst(_dp-
> > >mst_mgr,
> > -   intel_dp-
> > >is_mst);
> > -   goto put_power;
> > -   }
> > +   if (intel_dp->is_mst) {
> > +   if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
> > +   /*
> > +    * If we were in MST mode, and device is not
> > +    * there, get out of MST mode
> > +    */
> > +   DRM_DEBUG_KMS("MST device may have disappeared %d vs
> > %d\n",
> > +     intel_dp->is_mst, intel_dp-
> > >mst_mgr.mst_state);
> > +   intel_dp->is_mst = false;
> > +   drm_dp_mst_topology_mgr_set_mst(_dp->mst_mgr,
> > +   intel_dp->is_mst);
> > +   intel_dp->detect_done = false;
> > +   goto put_power;
> >     }
> > +   }
> >  
> > -   if (!intel_dp->is_mst) {
> > -   if (!intel_dp_short_pulse(intel_dp)) {
> > -   intel_dp_long_pulse(intel_dp-
> > >attached_connector);
> > -   goto put_power;
> > -   }
> > +   if (!intel_dp->is_mst) {
> > +   if (!intel_dp_short_pulse(intel_dp)) {
> > +   intel_dp->detect_done = false;
> > +   goto put_power;
> >     }
> >     }
> >  

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] [PATCH 8/9] drm/i915: Add location of the Rcomp resistor to bxt_ddi_phy_info

[Ander Conselvan de Oliveira]

Use struct bxt_ddi_phy_info to hold information of where the Rcomp
resistor is located, instead of hard coding it in the init sequence.

Note that this moves the enabling of the phy with the Rcomp resistor out
of the power well enable code. That should be safe since
bxt_ddi_phy_init() is called while the power domains lock is held, and
that is the only way that function gets called, so there is no
possibility of a concurrent phy enable caused by a power domain get
call.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/intel_dpio_phy.c   | 76 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 15 ---
 2 files changed, 59 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c 
b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 66d750a..e8a75fd 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -124,6 +124,13 @@ struct bxt_ddi_phy_info {
bool dual_channel;
 
/**
+* @rcomp_phy: If -1, indicates this phy has its own rcomp resistor.
+* Otherwise the GRC value will be copied from the phy indicated by
+* this field.
+*/
+   enum dpio_phy rcomp_phy;
+
+   /**
 * @channel: struct containing per channel information.
 */
struct {
@@ -137,6 +144,7 @@ struct bxt_ddi_phy_info {
 static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
[DPIO_PHY0] = {
.dual_channel = true,
+   .rcomp_phy = DPIO_PHY1,
 
.channel = {
[DPIO_CH0] = { .port = PORT_B },
@@ -145,6 +153,7 @@ static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
},
[DPIO_PHY1] = {
.dual_channel = false,
+   .rcomp_phy = -1,
 
.channel = {
[DPIO_CH0] = { .port = PORT_A },
@@ -152,6 +161,7 @@ static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
},
 };
 
+static u32 bxt_phy_port_mask(const struct bxt_ddi_phy_info *phy_info)
 {
return (phy_info->dual_channel * BIT(phy_info->channel[DPIO_CH1].port)) 
|
BIT(phy_info->channel[DPIO_CH0].port);
@@ -199,6 +209,7 @@ void bxt_ddi_phy_set_signal_level(struct drm_i915_private 
*dev_priv,
 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
enum dpio_phy phy)
 {
+   const struct bxt_ddi_phy_info *phy_info = _ddi_phy_info[phy];
enum port port;
 
if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
@@ -212,9 +223,10 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private 
*dev_priv,
return false;
}
 
-   if (phy == DPIO_PHY1 &&
-   !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE)) {
-   DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't done\n");
+   if (phy_info->rcomp_phy == -1 &&
+   !(I915_READ(BXT_PORT_REF_DW3(phy)) & GRC_DONE)) {
+   DRM_DEBUG_DRIVER("DDI PHY %d powered, but GRC isn't done\n",
+phy);
 
return false;
}
@@ -259,14 +271,15 @@ static void bxt_phy_wait_grc_done(struct drm_i915_private 
*dev_priv,
DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
 }
 
-void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
+ enum dpio_phy phy)
 {
const struct bxt_ddi_phy_info *phy_info = _ddi_phy_info[phy];
u32 val;
 
if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
/* Still read out the GRC value for state verification */
-   if (phy == DPIO_PHY0)
+   if (phy_info->rcomp_phy != -1)
dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
 
if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
@@ -336,30 +349,32 @@ void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, 
enum dpio_phy phy)
val |= OCL2_LDOFUSE_PWR_DIS;
I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
 
-   if (phy == DPIO_PHY0) {
+   if (phy_info->rcomp_phy != -1) {
uint32_t grc_code;
/*
 * PHY0 isn't connected to an RCOMP resistor so copy over
 * the corresponding calibrated value from PHY1, and disable
 * the automatic calibration on PHY0.
 */
-   val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, DPIO_PHY1);
+   val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv,
+ phy_info->rcomp_phy);
grc_code = val << GRC_CODE_FAST_SHIFT |
   val << GRC_CODE_SLOW_SHIFT |
   val;
-   I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
+ 

[Intel-gfx] [PATCH 7/9] drm/i915: Create a struct to hold information about the broxton phys

[Ander Conselvan de Oliveira]

Information about which phy is dual channel is hardcoded in the phy init
sequence. Split that to a separate struct so the init sequence is more
generic.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/i915_reg.h   |  9 +++--
 drivers/gpu/drm/i915/intel_dpio_phy.c | 63 +--
 2 files changed, 60 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f6d29fb..d3802c6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1308,8 +1308,13 @@ enum skl_disp_power_wells {
 #define BXT_PORT_CL1CM_DW30(phy)   _BXT_PHY((phy), _PORT_CL1CM_DW30_BC, \
_PORT_CL1CM_DW30_A)
 
-/* Defined for PHY0 only */
-#define BXT_PORT_CL2CM_DW6_BC  _MMIO(0x6C358)
+/* The spec defines this only for BXT PHY0, but lets assume that this
+ * would exist for PHY1 too if it had a second channel.
+ */
+#define _PORT_CL2CM_DW6_A  0x162358
+#define _PORT_CL2CM_DW6_BC 0x6C358
+#define BXT_PORT_CL2CM_DW6(phy)_BXT_PHY((phy), 
_PORT_CL2CM_DW6_BC, \
+   _PORT_CL2CM_DW6_A)
 #define   DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
 
 /* BXT PHY Ref registers */
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c 
b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 2a18724..66d750a 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -114,6 +114,49 @@
  * -
  */
 
+/**
+ * struct bxt_ddi_phy_info - Hold info for a broxton DDI phy
+ */
+struct bxt_ddi_phy_info {
+   /**
+* @dual_channel: true if this phy has a second channel.
+*/
+   bool dual_channel;
+
+   /**
+* @channel: struct containing per channel information.
+*/
+   struct {
+   /**
+* @port: which port maps to this channel.
+*/
+   enum port port;
+   } channel[2];
+};
+
+static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
+   [DPIO_PHY0] = {
+   .dual_channel = true,
+
+   .channel = {
+   [DPIO_CH0] = { .port = PORT_B },
+   [DPIO_CH1] = { .port = PORT_C },
+   }
+   },
+   [DPIO_PHY1] = {
+   .dual_channel = false,
+
+   .channel = {
+   [DPIO_CH0] = { .port = PORT_A },
+   }
+   },
+};
+
+{
+   return (phy_info->dual_channel * BIT(phy_info->channel[DPIO_CH1].port)) 
|
+   BIT(phy_info->channel[DPIO_CH0].port);
+}
+
 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
  enum port port, u32 margin, u32 scale,
  u32 enable, u32 deemphasis)
@@ -183,9 +226,7 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private 
*dev_priv,
return false;
}
 
-   for_each_port_masked(port,
-phy == DPIO_PHY0 ? BIT(PORT_B) | BIT(PORT_C) :
-   BIT(PORT_A)) {
+   for_each_port_masked(port, bxt_phy_port_mask(phy_info)) {
u32 tmp = I915_READ(BXT_PHY_CTL(port));
 
if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
@@ -220,6 +261,7 @@ static void bxt_phy_wait_grc_done(struct drm_i915_private 
*dev_priv,
 
 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
 {
+   const struct bxt_ddi_phy_info *phy_info = _ddi_phy_info[phy];
u32 val;
 
if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
@@ -272,10 +314,10 @@ void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, 
enum dpio_phy phy)
SUS_CLK_CONFIG;
I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
 
-   if (phy == DPIO_PHY0) {
-   val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
+   if (phy_info->dual_channel) {
+   val = I915_READ(BXT_PORT_CL2CM_DW6(phy));
val |= DW6_OLDO_DYN_PWR_DOWN_EN;
-   I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
+   I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val);
}
 
val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
@@ -290,7 +332,7 @@ void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, 
enum dpio_phy phy)
 * FIXME: Clarify programming of the following, the register is
 * read-only with bit 6 fixed at 0 at least in stepping A.
 */
-   if (phy == DPIO_PHY1)
+   if (!phy_info->dual_channel)
val |= OCL2_LDOFUSE_PWR_DIS;
I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
 
@@ -363,6 +405,7 @@ __phy_reg_verify_state(struct drm_i915_private *dev_priv, 
enum dpio_phy phy,
 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
  enum dpio_phy phy)
 {
+   const struct 

[Intel-gfx] [PATCH 0/9] Broxton ddi phy refactoring

[Ander Conselvan de Oliveira]

Hi,

This is a small refactoring of the broxton ddi phy code that splits the
knowledge of each phy's configuration from the code itself and makes
the connection between the ports and the channels in the phy more
obvious.

I took the oppurtunity to move the code to intel_dpio_phy.c, since there
are a lot of similarities between the bxt and chv phys, as evidenced by
the documentation.

Thanks,
Ander

Ander Conselvan de Oliveira (9):
  drm/i915: Rename struct i915_power_well field data to id
  drm/i915: Explicitly map broxton DPIO power wells to phys
  drm/i915: Pass lane count to bxt_ddi_phy_calc_lane_optmin_mask()
  drm/i915: Move broxton phy code to intel_dpio_phy.c
  drm/i915: Move DPIO phy documentation section to intel_dpio_phy.c
  drm/i915: Move broxton vswing sequence to intel_dpio_phy.c
  drm/i915: Create a struct to hold information about the broxton phys
  drm/i915: Add location of the Rcomp resistor to bxt_ddi_phy_info
  drm/i915: Address broxton phy registers based on phy and channel
number

 Documentation/gpu/i915.rst  |   2 +-
 drivers/gpu/drm/i915/i915_drv.h |  23 ++
 drivers/gpu/drm/i915/i915_reg.h | 303 +---
 drivers/gpu/drm/i915/intel_ddi.c| 362 +--
 drivers/gpu/drm/i915/intel_dpio_phy.c   | 597 
 drivers/gpu/drm/i915/intel_dpll_mgr.c   |  84 +++--
 drivers/gpu/drm/i915/intel_drv.h|   6 -
 drivers/gpu/drm/i915/intel_runtime_pm.c | 145 
 8 files changed, 821 insertions(+), 701 deletions(-)

-- 
2.5.5

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[Intel-gfx] [PATCH 5/9] drm/i915: Move DPIO phy documentation section to intel_dpio_phy.c

[Ander Conselvan de Oliveira]

Move the DPIO phy documentation section to intel_dpio_phy.c, since that
is a more suitable place now that there is a source file dedicated for
those phys.

Signed-off-by: Ander Conselvan de Oliveira 

---
 Documentation/gpu/i915.rst|  2 +-
 drivers/gpu/drm/i915/i915_reg.h   | 91 +--
 drivers/gpu/drm/i915/intel_dpio_phy.c | 91 +++
 3 files changed, 93 insertions(+), 91 deletions(-)

diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 87aaffc..8cecae1 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -180,7 +180,7 @@ Display Refresh Rate Switching (DRRS)
 DPIO
 
 
-.. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h
+.. kernel-doc:: drivers/gpu/drm/i915/intel_dpio_phy.c
:doc: DPIO
 
 CSR firmware support for DMC
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index acc767a..f6d29fb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -831,96 +831,7 @@ enum skl_disp_power_wells {
 #define  CCK_FREQUENCY_STATUS_SHIFT8
 #define  CCK_FREQUENCY_VALUES  (0x1f << 0)
 
-/**
- * DOC: DPIO
- *
- * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
- * ports. DPIO is the name given to such a display PHY. These PHYs
- * don't follow the standard programming model using direct MMIO
- * registers, and instead their registers must be accessed trough IOSF
- * sideband. VLV has one such PHY for driving ports B and C, and CHV
- * adds another PHY for driving port D. Each PHY responds to specific
- * IOSF-SB port.
- *
- * Each display PHY is made up of one or two channels. Each channel
- * houses a common lane part which contains the PLL and other common
- * logic. CH0 common lane also contains the IOSF-SB logic for the
- * Common Register Interface (CRI) ie. the DPIO registers. CRI clock
- * must be running when any DPIO registers are accessed.
- *
- * In addition to having their own registers, the PHYs are also
- * controlled through some dedicated signals from the display
- * controller. These include PLL reference clock enable, PLL enable,
- * and CRI clock selection, for example.
- *
- * Eeach channel also has two splines (also called data lanes), and
- * each spline is made up of one Physical Access Coding Sub-Layer
- * (PCS) block and two TX lanes. So each channel has two PCS blocks
- * and four TX lanes. The TX lanes are used as DP lanes or TMDS
- * data/clock pairs depending on the output type.
- *
- * Additionally the PHY also contains an AUX lane with AUX blocks
- * for each channel. This is used for DP AUX communication, but
- * this fact isn't really relevant for the driver since AUX is
- * controlled from the display controller side. No DPIO registers
- * need to be accessed during AUX communication,
- *
- * Generally on VLV/CHV the common lane corresponds to the pipe and
- * the spline (PCS/TX) corresponds to the port.
- *
- * For dual channel PHY (VLV/CHV):
- *
- *  pipe A == CMN/PLL/REF CH0
- *
- *  pipe B == CMN/PLL/REF CH1
- *
- *  port B == PCS/TX CH0
- *
- *  port C == PCS/TX CH1
- *
- * This is especially important when we cross the streams
- * ie. drive port B with pipe B, or port C with pipe A.
- *
- * For single channel PHY (CHV):
- *
- *  pipe C == CMN/PLL/REF CH0
- *
- *  port D == PCS/TX CH0
- *
- * On BXT the entire PHY channel corresponds to the port. That means
- * the PLL is also now associated with the port rather than the pipe,
- * and so the clock needs to be routed to the appropriate transcoder.
- * Port A PLL is directly connected to transcoder EDP and port B/C
- * PLLs can be routed to any transcoder A/B/C.
- *
- * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
- * digital port D (CHV) or port A (BXT). ::
- *
- *
- * Dual channel PHY (VLV/CHV/BXT)
- * -
- * |  CH0  |  CH1  |
- * |  CMN/PLL/REF  |  CMN/PLL/REF  |
- * |---|---| Display PHY
- * | PCS01 | PCS23 | PCS01 | PCS23 |
- * |---|---|---|---|
- * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
- * -
- * | DDI0  | DDI1  | DP/HDMI ports
- * -
- *
- * Single channel PHY (CHV/BXT)
- * -
- * |  CH0  |
- * |  CMN/PLL/REF  |
- * |---| Display PHY
- * | PCS01 | PCS23 |
- * |---|---|
- * |TX0|TX1|TX2|TX3|
- * -
- * | DDI2  | DP/HDMI port
- * -
- */
+/* DPIO registers */
 #define DPIO_DEVFN 0
 
 #define DPIO_CTL   _MMIO(VLV_DISPLAY_BASE + 0x2110)
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c 
b/drivers/gpu/drm/i915/intel_dpio_phy.c
index edf0cfd..6806296 100644
--- 

[Intel-gfx] [PATCH 2/9] drm/i915: Explicitly map broxton DPIO power wells to phys

[Ander Conselvan de Oliveira]

The mapping from the BXT_DPIO_CMN_* power wells to their respective phys
required a detour implemented in the bxt_power_well_to_phy() function.
Instead, embed that information directly into the power_well struct, by
resurrecting the data field.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/i915_drv.h |  5 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 22 +++---
 2 files changed, 12 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5bd3f59..93c90b9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1318,6 +1318,11 @@ struct i915_power_well {
unsigned long domains;
/* unique identifier for this power well */
unsigned long id;
+   /*
+* Arbitraty data associated with this power well. Platform and power
+* well specific.
+*/
+   unsigned long data;
const struct i915_power_well_ops *ops;
 };
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 4ecaf6a..d41fd46 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -846,13 +846,6 @@ static void skl_power_well_disable(struct drm_i915_private 
*dev_priv,
skl_set_power_well(dev_priv, power_well, false);
 }
 
-static enum dpio_phy bxt_power_well_to_phy(struct i915_power_well *power_well)
-{
-   enum skl_disp_power_wells power_well_id = power_well->id;
-
-   return power_well_id == BXT_DPIO_CMN_A ? DPIO_PHY1 : DPIO_PHY0;
-}
-
 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
   struct i915_power_well *power_well)
 {
@@ -868,7 +861,7 @@ static void bxt_dpio_cmn_power_well_enable(struct 
drm_i915_private *dev_priv,
intel_power_well_get(dev_priv, cmn_a_well);
}
 
-   bxt_ddi_phy_init(dev_priv, bxt_power_well_to_phy(power_well));
+   bxt_ddi_phy_init(dev_priv, power_well->data);
 
if (cmn_a_well)
intel_power_well_put(dev_priv, cmn_a_well);
@@ -877,14 +870,13 @@ static void bxt_dpio_cmn_power_well_enable(struct 
drm_i915_private *dev_priv,
 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
 {
-   bxt_ddi_phy_uninit(dev_priv, bxt_power_well_to_phy(power_well));
+   bxt_ddi_phy_uninit(dev_priv, power_well->data);
 }
 
 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
 {
-   return bxt_ddi_phy_is_enabled(dev_priv,
- bxt_power_well_to_phy(power_well));
+   return bxt_ddi_phy_is_enabled(dev_priv, power_well->data);
 }
 
 static void bxt_dpio_cmn_power_well_sync_hw(struct drm_i915_private *dev_priv,
@@ -903,13 +895,11 @@ static void bxt_verify_ddi_phy_power_wells(struct 
drm_i915_private *dev_priv)
 
power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
if (power_well->count > 0)
-   bxt_ddi_phy_verify_state(dev_priv,
-bxt_power_well_to_phy(power_well));
+   bxt_ddi_phy_verify_state(dev_priv, power_well->data);
 
power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC);
if (power_well->count > 0)
-   bxt_ddi_phy_verify_state(dev_priv,
-bxt_power_well_to_phy(power_well));
+   bxt_ddi_phy_verify_state(dev_priv, power_well->data);
 }
 
 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
@@ -2163,12 +2153,14 @@ static struct i915_power_well bxt_power_wells[] = {
.domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
.ops = _dpio_cmn_power_well_ops,
.id = BXT_DPIO_CMN_A,
+   .data = DPIO_PHY1,
},
{
.name = "dpio-common-bc",
.domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
.ops = _dpio_cmn_power_well_ops,
.id = BXT_DPIO_CMN_BC,
+   .data = DPIO_PHY0,
},
 };
 
-- 
2.5.5

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Re: [Intel-gfx] [PATCH 2/3] drm/i915/gtt: Free unused lower-level page tables

[Chris Wilson]

On Wed, Oct 05, 2016 at 09:40:48AM +0300, Joonas Lahtinen wrote:
> On ti, 2016-10-04 at 15:54 +0200, Michał Winiarski wrote:
> > Since "Dynamic page table allocations" were introduced, our page tables
> > can grow (being dynamically allocated) with address space range usage.
> > Unfortunately, their lifetime is bound to vm. This is not a huge problem
> > when we're not using softpin - drm_mm is creating an upper bound on used
> > range by causing addresses for our VMAs to eventually be reused.
> > 
> > With softpin, long lived contexts can drain the system out of memory
> > even with a single "small" object. For example:
> > 
> > bo = bo_alloc(size);
> > while(true)
> > offset += size;
> > exec(bo, offset);
> > 
> > Will cause us to create new allocations until all memory in the system
> > is used for tracking GPU pages (even though almost all PTEs in this vm
> > are pointing to scratch).
> > 
> > Let's free unused page tables in clear_range to prevent this - if no
> > entries are used, we can safely free it and return this information to
> > the caller (so that higher-level entry is pointing to scratch).
> > 
> 
> Sounds like this could and should have a I-G-T testcase, right?

The problem is that tables are internal to the driver. The user visible
impact is premature oom due to kernel bloat. We could dump the ppgtt to
userpsace and assert that entries we have closed are unused, but that
would be a fragile test for one particular implementation.

gem_exec_alignment will oom quite happily at the moment due to the
bitmap allocation (once we have the u64 alignment fixes reviewed and
upsteamed at least). Simply for that reason I want to completely
erradicate the bitmaps - they are not used for anything. The valid
range intersection we already know, and here the use as to whether a
particular level is empty is a simple counter.
-Chris

-- 
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Re: [Intel-gfx] [PATCH v3] drm/i915/bxt: Broxton decoupled MMIO

[Praveen Paneri]

Hi Chris,

On Wednesday 05 October 2016 01:26 AM, Chris Wilson wrote:

On Tue, Oct 04, 2016 at 09:16:06PM +0530, Praveen Paneri wrote:

+#define HAS_DECOUPLED_MMIO(dev) (INTEL_INFO(dev)->has_decoupled_mmio \
+   && IS_BXT_REVID(dev, BXT_REVID_C0, REVID_FOREVER))


Edit dev_priv->info.has_decoupled_mmio on init.
Can I add this check directly into __intel_uncore_early_sanitize(), like 
below?


@@ -419,6 +419,10 @@ static void __intel_uncore_early_sanitize(struct 
drm_i915_private *dev_priv,

   GT_FIFO_CTL_RC6_POLICY_STALL);
}

+   /* Enable Decoupled MMIO only on BXT C stepping onwards */
+   if (!IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
+   info->has_decoupled_mmio = 0;
+
intel_uncore_forcewake_reset(dev_priv, restore_forcewake);
 }




+static void __gen9_decoupled_mmio_access(struct drm_i915_private *dev_priv,
+u32 reg,
+enum forcewake_domains fw_engine,
+enum decoupled_ops operation)
+{
+   enum decoupled_power_domains dpd_engine;
+   u32 ctrl_reg_data = 0;
+
+   dpd_engine = fw2dpd_engine[fw_engine - 1];


enum decoupled_power_domains dpd = fw2dpd_engine[fw_engine - 1];

enum decoupled_power_domain

And don't call it fw_engine. fw_domain, if you must.
I can change it but related existing code still uses fw_engine. Wouldn't 
it look out of the place?


Thanks,
Praveen



+
+   ctrl_reg_data |= reg;
+   ctrl_reg_data |= (operation << GEN9_DECOUPLED_OP_SHIFT);
+   ctrl_reg_data |= (dpd_engine << GEN9_DECOUPLED_PD_SHIFT);
+   __raw_i915_write32(dev_priv, GEN9_DECOUPLED_REG0_DW1, ctrl_reg_data);
+
+   ctrl_reg_data |= GEN9_DECOUPLED_DW1_GO;
+   __raw_i915_write32(dev_priv, GEN9_DECOUPLED_REG0_DW1, ctrl_reg_data);
+
+   if (wait_for_atomic((__raw_i915_read32(dev_priv,
+   GEN9_DECOUPLED_REG0_DW1) & GEN9_DECOUPLED_DW1_GO) == 0,
+   FORCEWAKE_ACK_TIMEOUT_MS))
+   DRM_ERROR("Decoupled MMIO wait timed out\n");
+}
+
+static inline u32 __gen9_decoupled_mmio_read(struct drm_i915_private *dev_priv,
+  u32 reg,
+  enum forcewake_domains fw)


__gen9_decoupeld_mmio_read32()


+{
+   __gen9_decoupled_mmio_access(dev_priv,
+   reg,
+   fw_engine,
+   GEN9_DECOUPLED_OP_READ);


__gen9_decoupled_mmio_access(dev_priv, reg, fw, GEN9_DECOUPLED_OP_READ);


+
+   return __raw_i915_read32(dev_priv,
+   GEN9_DECOUPLED_REG0_DW0);


Everywhere! Please be careful with alignment.


+#define __gen9_decoupled_read(x) \
+static u##x \
+gen9_decoupled_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool 
trace) { \
+   enum forcewake_domains fw_engine; \
+   GEN6_READ_HEADER(x); \
+   fw_engine = __fwtable_reg_read_fw_domains(offset); \
+   if (!fw_engine || !(fw_engine & ~dev_priv->uncore.fw_domains_active)) { 
\
+   val = __raw_i915_read##x(dev_priv, reg); \
+   } else { \
+   unsigned i; \
+   u32 *ptr_data = (u32 *)  \
+   for (i = 0; i < x/32; i++, offset += sizeof(u32), ptr_data++) \
+   *ptr_data = __gen9_decoupled_mmio_read(dev_priv, \
+offset, \
+fw_engine); \
+   } \
+   GEN6_READ_FOOTER; \
+}


Reverse it,

if (domain & ~dev_priv->uncore.fw_domains_active) {
u32 *ptr = (u32 *)
unsigned i;

for (i = 0; i < x/32; i++, offset += sizeof(u32), ptr++)
*ptr = __gen9_decoupled_mmio_read32(dev_priv, offset, 
domain);
} else {
val = __raw_i915_read##x(dev_priv, reg);
}


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Re: [Intel-gfx] [PATCH igt 2/2] tests/gem_exec_suspend: Add basic s4-devices subtest

[Chris Wilson]

On Wed, Oct 05, 2016 at 12:04:53PM +0300, Imre Deak wrote:
> Add a new subtest that performs suspend-to-disk, but instead of doing
> the full sequence it suspends/resumes only devices. A failed s4 subtest
> and a successful s4-devices subtest would indicate a kernel core or BIOS
> problem as opposed to some issue in the driver.

Worth doing for suspend as well? Same argument for easier diagnosis of
any problem.
 
> Signed-off-by: Imre Deak 

Looks sensible to me.
-Chris

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Re: [Intel-gfx] [PATCH 2/3] drm/i915/gtt: Free unused lower-level page tables

[Joonas Lahtinen]

On ti, 2016-10-04 at 15:54 +0200, Michał Winiarski wrote:
> Since "Dynamic page table allocations" were introduced, our page tables
> can grow (being dynamically allocated) with address space range usage.
> Unfortunately, their lifetime is bound to vm. This is not a huge problem
> when we're not using softpin - drm_mm is creating an upper bound on used
> range by causing addresses for our VMAs to eventually be reused.
> 
> With softpin, long lived contexts can drain the system out of memory
> even with a single "small" object. For example:
> 
> bo = bo_alloc(size);
> while(true)
> offset += size;
> exec(bo, offset);
> 
> Will cause us to create new allocations until all memory in the system
> is used for tracking GPU pages (even though almost all PTEs in this vm
> are pointing to scratch).
> 
> Let's free unused page tables in clear_range to prevent this - if no
> entries are used, we can safely free it and return this information to
> the caller (so that higher-level entry is pointing to scratch).
> 

Sounds like this could and should have a I-G-T testcase, right?
 
> @@ -706,7 +710,7 @@ static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
>   return gen8_write_pdp(req, 0, px_dma(>pml4));
>  }
>  
> -static void gen8_ppgtt_clear_pt(struct i915_address_space *vm,

Add comment for non-obvious bool return value.

> +static bool gen8_ppgtt_clear_pt(struct i915_address_space *vm,
>   struct i915_page_table *pt,
>   uint64_t start,
>   uint64_t length,
> @@ -724,50 +728,102 @@ static void gen8_ppgtt_clear_pt(struct 
> i915_address_space *vm,
>    I915_CACHE_LLC, use_scratch);
>  
>   if (WARN_ON(!px_page(pt)))
> - return;
> + return false;
>  
>   bitmap_clear(pt->used_ptes, pte_start, num_entries);
>  
> + if (bitmap_empty(pt->used_ptes, GEN8_PTES)) {
> + free_pt(vm->dev, pt);

Maybe the caller should do the free_pt()? If kept here, should at least
be clearly documented.

Other than those, looks like good improvements to me.

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Remove unused "valid" parameter from pte_encode

[Mika Kuoppala]

Michał Winiarski  writes:

> We're no longer using any invalid PTEs - everything that's not used
> should be pointing to scratch.
>

I was about to suggest this before patch 2/3 to make it simpler.

For historical context: https://patchwork.kernel.org/patch/9135411/

I would amend the commit message a little. 'We're no longer using'
suggests that we changed recently/by earlier commits how we map
into the invalid ptes.

I think it has always been the case that we map to valid==scratch.

Lets try to distill the reasoning from Chris Wilson's reply
for future reader, something like:

'We never used any invalid ptes, as those were put in place for a
possibility of doing gpu faults. However our batchbuffers are
not restricted in length, so everything needs to be pointing to
something and thus out-of-bounds pointing to scratch. Remove the
valid flag as it is always true.'

That message conveyed with perhaps better wording/english,
and you can add my,
Reviewed-by: Mika Kuoppala 

-Mika

> Cc: Chris Wilson 
> Cc: Joonas Lahtinen 
> Cc: Michel Thierry 
> Cc: Mika Kuoppala 
> Signed-off-by: Michał Winiarski 
> ---
>  drivers/gpu/drm/i915/i915_gem.c|   6 +-
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c |   3 +-
>  drivers/gpu/drm/i915/i915_gem_gtt.c| 154 
> +++--
>  drivers/gpu/drm/i915/i915_gem_gtt.h|   5 +-
>  4 files changed, 65 insertions(+), 103 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 1418c1c..b344340 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -919,8 +919,7 @@ out_unpin:
>   if (node.allocated) {
>   wmb();
>   ggtt->base.clear_range(>base,
> -node.start, node.size,
> -true);
> +node.start, node.size);
>   i915_gem_object_unpin_pages(obj);
>   remove_mappable_node();
>   } else {
> @@ -1228,8 +1227,7 @@ out_unpin:
>   if (node.allocated) {
>   wmb();
>   ggtt->base.clear_range(>base,
> -node.start, node.size,
> -true);
> +node.start, node.size);
>   i915_gem_object_unpin_pages(obj);
>   remove_mappable_node();
>   } else {
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
> b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index 33c8522..54b091b 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -370,8 +370,7 @@ static void reloc_cache_fini(struct reloc_cache *cache)
>  
>   ggtt->base.clear_range(>base,
>  cache->node.start,
> -cache->node.size,
> -true);
> +cache->node.size);
>   drm_mm_remove_node(>node);
>   } else {
>   i915_vma_unpin((struct i915_vma *)cache->node.mm);
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 281e349..fa78bb1 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -191,15 +191,13 @@ static void ppgtt_unbind_vma(struct i915_vma *vma)
>  {
>   vma->vm->clear_range(vma->vm,
>vma->node.start,
> -  vma->size,
> -  true);
> +  vma->size);
>  }
>  
>  static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
> -   enum i915_cache_level level,
> -   bool valid)
> +   enum i915_cache_level level)
>  {
> - gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
> + gen8_pte_t pte = _PAGE_PRESENT | _PAGE_RW;
>   pte |= addr;
>  
>   switch (level) {
> @@ -218,10 +216,9 @@ static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
>  }
>  
>  static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
> -   const enum i915_cache_level level,
> -   bool valid)
> +   const enum i915_cache_level level)
>  {
> - gen8_pde_t pde = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
> + gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
>   pde |= addr;
>   if (level != I915_CACHE_NONE)
>   pde |= PPAT_CACHED_PDE_INDEX;
> @@ -235,9 +232,9 @@ static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
>  
>  static gen6_pte_t snb_pte_encode(dma_addr_t addr,
>  

[Intel-gfx] [PATCH igt 2/2] tests/gem_exec_suspend: Add basic s4-devices subtest

[Imre Deak]

Add a new subtest that performs suspend-to-disk, but instead of doing
the full sequence it suspends/resumes only devices. A failed s4 subtest
and a successful s4-devices subtest would indicate a kernel core or BIOS
problem as opposed to some issue in the driver.

Signed-off-by: Imre Deak 
---
 tests/gem_exec_suspend.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/tests/gem_exec_suspend.c b/tests/gem_exec_suspend.c
index b953afb..e85d877 100644
--- a/tests/gem_exec_suspend.c
+++ b/tests/gem_exec_suspend.c
@@ -32,7 +32,8 @@
 
 #define NOSLEEP 0
 #define SUSPEND 1
-#define HIBERNATE 2
+#define HIBERNATE_DEVICES 3
+#define HIBERNATE 4
 #define mode(x) ((x) & 0xff)
 
 #define LOCAL_I915_EXEC_BSD_SHIFT  (13)
@@ -210,6 +211,11 @@ static void run_test(int fd, unsigned engine, unsigned 
flags)
  SUSPEND_TEST_NONE);
break;
 
+   case HIBERNATE_DEVICES:
+   igt_system_suspend_autoresume(SUSPEND_STATE_DISK,
+ SUSPEND_TEST_DEVICES);
+   break;
+
case HIBERNATE:
igt_system_suspend_autoresume(SUSPEND_STATE_DISK,
  SUSPEND_TEST_NONE);
@@ -250,6 +256,8 @@ igt_main
run_test(fd, -1, NOSLEEP);
igt_subtest("basic-S3")
run_test(fd, -1, SUSPEND);
+   igt_subtest("basic-S4-devices")
+   run_test(fd, -1, HIBERNATE_DEVICES);
igt_subtest("basic-S4")
run_test(fd, -1, HIBERNATE);
 
-- 
2.5.0

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[Intel-gfx] [PATCH igt 1/2] lib/igt_aux: Add support for various system suspend/resume options

[Imre Deak]

To have a more accurate idea about any suspend/resume issues we can
perform the s/r until various phases in the s/r sequence. This way we
can isolate the given problem as being a device driver, kernel core or
BIOS related issue. Actual subtests using these new s/r phases will be
added as follow-up.

While at it also add the freeze suspend target, it's something we also
would need to test.

Signed-off-by: Imre Deak 
---
 lib/igt_aux.c| 172 ++-
 lib/igt_aux.h|  24 +-
 tests/drv_suspend.c  |  24 --
 tests/gem_exec_suspend.c |   6 +-
 tests/gem_mocs_settings.c|  24 --
 tests/gem_ringfill.c |   6 +-
 tests/gem_softpin.c  |   6 +-
 tests/gem_stolen.c   |   2 +-
 tests/gem_workarounds.c  |   2 +-
 tests/kms_cursor_crc.c   |   3 +-
 tests/kms_fbcon_fbt.c|   6 +-
 tests/kms_flip.c |   3 +-
 tests/kms_frontbuffer_tracking.c |   4 +-
 tests/kms_pipe_crc_basic.c   |   3 +-
 tests/kms_plane.c|   3 +-
 tests/kms_psr_sink_crc.c |   6 +-
 tests/pm_rpm.c   |   6 +-
 17 files changed, 224 insertions(+), 76 deletions(-)

diff --git a/lib/igt_aux.c b/lib/igt_aux.c
index 5eaf35e..ba4dbf7 100644
--- a/lib/igt_aux.c
+++ b/lib/igt_aux.c
@@ -63,6 +63,7 @@
 #include "ioctl_wrappers.h"
 #include "igt_kms.h"
 #include "igt_stats.h"
+#include "igt_sysfs.h"
 
 /**
  * SECTION:igt_aux
@@ -625,60 +626,157 @@ void igt_cleanup_aperture_trashers(void)
free(trash_bos);
 }
 
+static const char *suspend_state_name[] = {
+   [SUSPEND_STATE_FREEZE] = "freeze",
+   [SUSPEND_STATE_MEM] = "mem",
+   [SUSPEND_STATE_DISK] = "disk",
+};
+
+static const char *suspend_test_name[] = {
+   [SUSPEND_TEST_NONE] = "none",
+   [SUSPEND_TEST_FREEZER] = "freezer",
+   [SUSPEND_TEST_DEVICES] = "devices",
+   [SUSPEND_TEST_PLATFORM] = "platform",
+   [SUSPEND_TEST_PROCESSORS] = "processors",
+   [SUSPEND_TEST_CORE] = "core",
+};
+
+static enum igt_suspend_test get_suspend_test(int power_dir)
+{
+   char *test_line;
+   char *test_name;
+   enum igt_suspend_test test;
+
+   if (faccessat(power_dir, "pm_test", R_OK, 0))
+   return SUSPEND_TEST_NONE;
+
+   igt_assert((test_line = igt_sysfs_get(power_dir, "pm_test")));
+   for (test_name = strtok(test_line, " "); test_name;
+test_name = strtok(NULL, " "))
+   if (test_name[0] == '[') {
+   test_name[strlen(test_name) - 1] = '\0';
+   test_name++;
+   break;
+   }
+
+   for (test = SUSPEND_TEST_NONE; test < SUSPEND_TEST_NUM; test++)
+   if (strcmp(suspend_test_name[test], test_name) == 0)
+   break;
+
+   igt_assert(test < SUSPEND_TEST_NUM);
+
+   free(test_line);
+
+   return test;
+}
+
+static void set_suspend_test(int power_dir, enum igt_suspend_test test)
+{
+   igt_assert(test < SUSPEND_TEST_NUM);
+
+   if (faccessat(power_dir, "pm_test", W_OK, 0)) {
+   igt_require(test == SUSPEND_TEST_NONE);
+   return;
+   }
+
+   igt_assert(igt_sysfs_set(power_dir, "pm_test", 
suspend_test_name[test]));
+}
+
 #define SQUELCH ">/dev/null 2>&1"
 
+static void suspend_via_rtcwake(enum igt_suspend_state state)
+{
+   char cmd[128];
+   int delay;
+
+   igt_assert(state < SUSPEND_STATE_NUM);
+
+   delay = state == SUSPEND_STATE_DISK ? 30 : 15;
+
+   /*
+* Skip if rtcwake would fail for a reason not related to the kernel's
+* suspend functionality.
+*/
+   snprintf(cmd, sizeof(cmd), "rtcwake -n -s %d -m %s " SQUELCH,
+delay, suspend_state_name[state]);
+   igt_require(system(cmd) == 0);
+
+   snprintf(cmd, sizeof(cmd), "rtcwake -s %d -m %s ",
+delay, suspend_state_name[state]);
+   igt_assert_f(system(cmd) == 0,
+"This failure means that something is wrong with "
+"the rtcwake tool or how your distro is set up. "
+"This is not a i915.ko or i-g-t bug.\n");
+}
+
+static void suspend_via_sysfs(int power_dir, enum igt_suspend_state state)
+{
+   igt_assert(state < SUSPEND_STATE_NUM);
+   igt_assert(igt_sysfs_set(power_dir, "state",
+suspend_state_name[state]));
+}
+
+static uint32_t get_supported_suspend_states(int power_dir)
+{
+   char *states;
+   char *state_name;
+   uint32_t state_mask;
+
+   igt_assert((states = igt_sysfs_get(power_dir, "state")));
+   state_mask = 0;
+   for (state_name = strtok(states, " "); state_name;
+state_name = strtok(NULL, " ")) {
+   enum igt_suspend_state state;
+
+   for (state = SUSPEND_STATE_FREEZE; state < SUSPEND_STATE_NUM;
+ 

[Intel-gfx] [PATCH 21/22] drm/i915: Make INTEL_GEN only take dev_priv

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Saves 968 bytes of .rodata strings.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.h  | 2 +-
 drivers/gpu/drm/i915/i915_gem_render_state.c | 6 +++---
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 drivers/gpu/drm/i915/intel_sprite.c  | 8 
 4 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1ec5560eadd3..a7e68beac570 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2606,8 +2606,8 @@ struct drm_i915_cmd_table {
__p; \
 })
 #define INTEL_INFO(p)  (&__I915__(p)->info)
-#define INTEL_GEN(p)   (INTEL_INFO(p)->gen)
 
+#define INTEL_GEN(dev_priv)(dev_priv->info.gen)
 #define INTEL_DEVID(dev_priv)  (dev_priv->info.device_id)
 
 #define REVID_FOREVER  0xff
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c 
b/drivers/gpu/drm/i915/i915_gem_render_state.c
index 95b7e9afd5f8..a98c0f42badd 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -72,9 +72,9 @@ render_state_get_rodata(const struct drm_i915_gem_request 
*req)
 
 static int render_state_setup(struct render_state *so)
 {
-   struct drm_device *dev = so->vma->vm->dev;
+   struct drm_i915_private *dev_priv = to_i915(so->vma->vm->dev);
const struct intel_renderstate_rodata *rodata = so->rodata;
-   const bool has_64bit_reloc = INTEL_GEN(dev) >= 8;
+   const bool has_64bit_reloc = INTEL_GEN(dev_priv) >= 8;
unsigned int i = 0, reloc_index = 0;
struct page *page;
u32 *d;
@@ -115,7 +115,7 @@ static int render_state_setup(struct render_state *so)
 
so->aux_batch_offset = i * sizeof(u32);
 
-   if (HAS_POOLED_EU(dev)) {
+   if (HAS_POOLED_EU(dev_priv)) {
/*
 * We always program 3x6 pool config but depending upon which
 * subslice is disabled HW drops down to appropriate config
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 0540afc3fef4..43343a9a07ef 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12449,7 +12449,7 @@ int intel_plane_atomic_calc_changes(struct 
drm_crtc_state *crtc_state,
struct drm_framebuffer *fb = plane_state->fb;
int ret;
 
-   if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
+   if (INTEL_GEN(dev_priv) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
ret = skl_update_scaler_plane(
to_intel_crtc_state(crtc_state),
to_intel_plane_state(plane_state));
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index f760d5fcbe48..8b4748839c07 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -753,7 +753,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
 struct intel_crtc_state *crtc_state,
 struct intel_plane_state *state)
 {
-   struct drm_device *dev = plane->dev;
+   struct drm_i915_private *dev_priv = to_i915(plane->dev);
struct drm_crtc *crtc = state->base.crtc;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_plane *intel_plane = to_intel_plane(plane);
@@ -797,7 +797,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
}
 
/* setup can_scale, min_scale, max_scale */
-   if (INTEL_INFO(dev)->gen >= 9) {
+   if (INTEL_GEN(dev_priv) >= 9) {
/* use scaler when colorkey is not required */
if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
can_scale = 1;
@@ -913,7 +913,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
 
width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
 
-   if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
+   if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 ||
width_bytes > 4096 || fb->pitches[0] > 4096)) {
DRM_DEBUG_KMS("Source dimensions exceed hardware 
limits\n");
return -EINVAL;
@@ -932,7 +932,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
dst->y1 = crtc_y;
dst->y2 = crtc_y + crtc_h;
 
-   if (INTEL_GEN(dev) >= 9) {
+   if (INTEL_GEN(dev_priv) >= 9) {
ret = skl_check_plane_surface(state);
if (ret)
return ret;
-- 
2.7.4

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[Intel-gfx] [PATCH 18/22] drm/i915: Make IS_G4X only take dev_priv

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Saves 472 bytes of .rodata strings.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.h|  2 +-
 drivers/gpu/drm/i915/i915_gem_stolen.c |  5 +++--
 drivers/gpu/drm/i915/i915_suspend.c|  4 ++--
 drivers/gpu/drm/i915/intel_crt.c   |  2 +-
 drivers/gpu/drm/i915/intel_display.c   | 40 ++
 drivers/gpu/drm/i915/intel_dp.c|  2 +-
 drivers/gpu/drm/i915/intel_hdmi.c  |  4 ++--
 drivers/gpu/drm/i915/intel_pm.c|  4 ++--
 8 files changed, 33 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 38f1d7b8121c..2162690ca44d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2651,7 +2651,7 @@ struct drm_i915_cmd_table {
 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
 #define IS_CRESTLINE(dev)  (INTEL_INFO(dev)->is_crestline)
 #define IS_GM45(dev_priv)  (INTEL_DEVID(dev_priv) == 0x2A42)
-#define IS_G4X(dev)(INTEL_INFO(dev)->is_g4x)
+#define IS_G4X(dev_priv)   (dev_priv->info.is_g4x)
 #define IS_PINEVIEW_G(dev_priv)(INTEL_DEVID(dev_priv) == 0xa001)
 #define IS_PINEVIEW_M(dev_priv)(INTEL_DEVID(dev_priv) == 0xa011)
 #define IS_PINEVIEW(dev)   (INTEL_INFO(dev)->is_pineview)
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c 
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 3508120b8c90..d1b40bce0249 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -204,7 +204,8 @@ static unsigned long i915_stolen_to_physical(struct 
drm_device *dev)
return 0;
 
/* make sure we don't clobber the GTT if it's within stolen memory */
-   if (INTEL_INFO(dev)->gen <= 4 && !IS_G33(dev) && !IS_G4X(dev)) {
+   if (INTEL_GEN(dev_priv) <= 4 && !IS_G33(dev_priv) &&
+   !IS_G4X(dev_priv)) {
struct {
u32 start, end;
} stolen[2] = {
@@ -437,7 +438,7 @@ int i915_gem_init_stolen(struct drm_device *dev)
case 3:
break;
case 4:
-   if (IS_G4X(dev))
+   if (IS_G4X(dev_priv))
g4x_get_stolen_reserved(dev_priv, _base,
_size);
break;
diff --git a/drivers/gpu/drm/i915/i915_suspend.c 
b/drivers/gpu/drm/i915/i915_suspend.c
index a0af170062b1..7870856fccd0 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -38,7 +38,7 @@ static void i915_save_display(struct drm_device *dev)
dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
 
/* save FBC interval */
-   if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
+   if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
 }
 
@@ -54,7 +54,7 @@ static void i915_restore_display(struct drm_device *dev)
intel_fbc_global_disable(dev_priv);
 
/* restore FBC interval */
-   if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
+   if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
 
i915_redisable_vga(dev);
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 8d1348f3880a..023fd84f8f7b 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -741,7 +741,7 @@ static int intel_crt_get_modes(struct drm_connector 
*connector)
 
i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
ret = intel_crt_ddc_get_modes(connector, i2c);
-   if (ret || !IS_G4X(dev))
+   if (ret || !IS_G4X(dev_priv))
goto out;
 
/* Try to probe digital port for output in DVI-I -> VGA mode. */
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index e11ed918a452..5ea07a1ac170 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3071,7 +3071,7 @@ static void i9xx_update_primary_plane(struct drm_plane 
*primary,
fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
dspcntr |= DISPPLANE_TILED;
 
-   if (IS_G4X(dev))
+   if (IS_G4X(dev_priv))
dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
 
intel_add_fb_offsets(, , plane_state, 0);
@@ -7223,7 +7223,7 @@ static int intel_crtc_compute_config(struct intel_crtc 
*crtc,
/* Cantiga+ cannot handle modes with a hsync front porch of 0.
 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
 */
-   if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
+   if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&

[Intel-gfx] [PATCH 08/22] drm/i915: Do not use INTEL_INFO(dev_priv)->ring_mask inside WARNs

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Saves 1520 bytes of .rodata strings.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index d00ec805f93d..9f3d6af9bbea 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -110,13 +110,14 @@ int intel_engines_init(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_device_info *device_info = mkwrite_device_info(dev_priv);
+   unsigned int ring_mask = INTEL_INFO(dev_priv)->ring_mask;
unsigned int mask = 0;
int (*init)(struct intel_engine_cs *engine);
unsigned int i;
int ret;
 
-   WARN_ON(INTEL_INFO(dev_priv)->ring_mask == 0);
-   WARN_ON(INTEL_INFO(dev_priv)->ring_mask &
+   WARN_ON(ring_mask == 0);
+   WARN_ON(ring_mask &
GENMASK(sizeof(mask) * BITS_PER_BYTE - 1, I915_NUM_ENGINES));
 
for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
@@ -143,7 +144,7 @@ int intel_engines_init(struct drm_device *dev)
 * are added to the driver by a warning and disabling the forgotten
 * engines.
 */
-   if (WARN_ON(mask != INTEL_INFO(dev_priv)->ring_mask))
+   if (WARN_ON(mask != ring_mask))
device_info->ring_mask = mask;
 
device_info->num_rings = hweight32(mask);
-- 
2.7.4

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[Intel-gfx] [PATCH 22/22] drm/i915: Make IS_GEN macros only take dev_priv

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Saves 1416 bytes of .rodata strings.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_debugfs.c|  4 +-
 drivers/gpu/drm/i915/i915_drv.c|  6 +--
 drivers/gpu/drm/i915/i915_drv.h| 16 +++---
 drivers/gpu/drm/i915/i915_gem.c|  8 +--
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |  4 +-
 drivers/gpu/drm/i915/i915_gem_fence.c  |  9 ++--
 drivers/gpu/drm/i915/i915_gem_gtt.c| 10 ++--
 drivers/gpu/drm/i915/i915_gem_stolen.c |  4 +-
 drivers/gpu/drm/i915/i915_gem_tiling.c |  4 +-
 drivers/gpu/drm/i915/i915_gpu_error.c  | 10 ++--
 drivers/gpu/drm/i915/i915_irq.c|  4 +-
 drivers/gpu/drm/i915/i915_suspend.c|  4 +-
 drivers/gpu/drm/i915/intel_crt.c   |  6 +--
 drivers/gpu/drm/i915/intel_display.c   | 41 ---
 drivers/gpu/drm/i915/intel_dp.c| 20 +++
 drivers/gpu/drm/i915/intel_drv.h   |  2 +-
 drivers/gpu/drm/i915/intel_fifo_underrun.c |  6 +--
 drivers/gpu/drm/i915/intel_guc_loader.c|  3 +-
 drivers/gpu/drm/i915/intel_lvds.c  |  2 +-
 drivers/gpu/drm/i915/intel_pm.c| 83 +++---
 drivers/gpu/drm/i915/intel_sprite.c|  4 +-
 21 files changed, 126 insertions(+), 124 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index dd6348cb43b3..2a46d0d1b0d4 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4554,7 +4554,7 @@ static void wm_latency_show(struct seq_file *m, const 
uint16_t wm[8])
else if (IS_VALLEYVIEW(dev_priv))
num_levels = 1;
else
-   num_levels = ilk_wm_max_level(dev) + 1;
+   num_levels = ilk_wm_max_level(dev_priv) + 1;
 
drm_modeset_lock_all(dev);
 
@@ -4670,7 +4670,7 @@ static ssize_t wm_latency_write(struct file *file, const 
char __user *ubuf,
else if (IS_VALLEYVIEW(dev_priv))
num_levels = 1;
else
-   num_levels = ilk_wm_max_level(dev) + 1;
+   num_levels = ilk_wm_max_level(dev_priv) + 1;
 
if (len >= sizeof(tmp))
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5e7b6a1cb2c8..c1956855feb6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -174,7 +174,7 @@ static void intel_detect_pch(struct drm_device *dev)
if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_IBX;
DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
-   WARN_ON(!IS_GEN5(dev));
+   WARN_ON(!IS_GEN5(dev_priv));
} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found CougarPoint PCH\n");
@@ -884,7 +884,7 @@ static int i915_mmio_setup(struct drm_device *dev)
int mmio_bar;
int mmio_size;
 
-   mmio_bar = IS_GEN2(dev) ? 1 : 0;
+   mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
/*
 * Before gen4, the registers and the GTT are behind different BARs.
 * However, from gen4 onwards, the registers and the GTT are shared
@@ -1037,7 +1037,7 @@ static int i915_driver_init_hw(struct drm_i915_private 
*dev_priv)
pci_set_master(pdev);
 
/* overlay on gen2 is broken and can't address above 1G */
-   if (IS_GEN2(dev)) {
+   if (IS_GEN2(dev_priv)) {
ret = dma_set_coherent_mask(>dev, DMA_BIT_MASK(30));
if (ret) {
DRM_ERROR("failed to set DMA mask\n");
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a7e68beac570..e01c818f9ca5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2744,14 +2744,14 @@ struct drm_i915_cmd_table {
  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
  * chips, etc.).
  */
-#define IS_GEN2(dev)   (!!(INTEL_INFO(dev)->gen_mask & BIT(1)))
-#define IS_GEN3(dev)   (!!(INTEL_INFO(dev)->gen_mask & BIT(2)))
-#define IS_GEN4(dev)   (!!(INTEL_INFO(dev)->gen_mask & BIT(3)))
-#define IS_GEN5(dev)   (!!(INTEL_INFO(dev)->gen_mask & BIT(4)))
-#define IS_GEN6(dev)   (!!(INTEL_INFO(dev)->gen_mask & BIT(5)))
-#define IS_GEN7(dev)   (!!(INTEL_INFO(dev)->gen_mask & BIT(6)))
-#define IS_GEN8(dev)   (!!(INTEL_INFO(dev)->gen_mask & BIT(7)))
-#define IS_GEN9(dev)   (!!(INTEL_INFO(dev)->gen_mask & BIT(8)))
+#define IS_GEN2(dev_priv)  (!!(dev_priv->info.gen_mask & BIT(1)))
+#define IS_GEN3(dev_priv)  (!!(dev_priv->info.gen_mask & BIT(2)))
+#define IS_GEN4(dev_priv)  (!!(dev_priv->info.gen_mask & BIT(3)))
+#define IS_GEN5(dev_priv)  (!!(dev_priv->info.gen_mask & BIT(4)))

[Intel-gfx] [PATCH 02/22] drm/i915: Shrink sdvo_cmd_names

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Pack the struct _sdvo_cmd_name to save 736 bytes of .rodata.

This is fine since the name pointers are used only for debug.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/intel_sdvo.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c 
b/drivers/gpu/drm/i915/intel_sdvo.c
index a061b0029797..9f352aac9526 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -307,7 +307,7 @@ static bool intel_sdvo_read_byte(struct intel_sdvo 
*intel_sdvo, u8 addr, u8 *ch)
 static const struct _sdvo_cmd_name {
u8 cmd;
const char *name;
-} sdvo_cmd_names[] = {
+} __attribute__ ((packed)) sdvo_cmd_names[] = {
SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
-- 
2.7.4

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[Intel-gfx] [PATCH 20/22] drm/i915: Make IS_VALLEYVIEW only take dev_priv

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Saves 944 bytes of .rodata strings and 128 bytes of .text.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 drivers/gpu/drm/i915/i915_gem_fence.c   | 2 +-
 drivers/gpu/drm/i915/i915_gpu_error.c   | 4 ++--
 drivers/gpu/drm/i915/intel_crt.c| 6 +++---
 drivers/gpu/drm/i915/intel_display.c| 6 +++---
 drivers/gpu/drm/i915/intel_dp.c | 8 
 drivers/gpu/drm/i915/intel_hdmi.c   | 2 +-
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +--
 9 files changed, 17 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 99e504703edd..1ec5560eadd3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2661,7 +2661,7 @@ struct drm_i915_cmd_table {
 #define IS_IVB_GT1(dev_priv)   (INTEL_DEVID(dev_priv) == 0x0156 || \
 INTEL_DEVID(dev_priv) == 0x0152 || \
 INTEL_DEVID(dev_priv) == 0x015a)
-#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
+#define IS_VALLEYVIEW(dev_priv)(dev_priv->info.is_valleyview)
 #define IS_CHERRYVIEW(dev_priv)(dev_priv->info.is_cherryview)
 #define IS_HASWELL(dev_priv)   (dev_priv->info.is_haswell)
 #define IS_BROADWELL(dev_priv) (dev_priv->info.is_broadwell)
diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c 
b/drivers/gpu/drm/i915/i915_gem_fence.c
index 8df1fa7234e8..d26768567252 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence.c
@@ -448,7 +448,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 
-   if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) {
+   if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) {
/*
 * On BDW+, swizzling is not used. We leave the CPU memory
 * controller in charge of optimizing memory accesses without
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 6c7b0f0341b5..d807b3f9a43b 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1351,7 +1351,7 @@ static void i915_capture_reg_state(struct 
drm_i915_private *dev_priv,
 */
 
/* 1: Registers specific to a single generation */
-   if (IS_VALLEYVIEW(dev)) {
+   if (IS_VALLEYVIEW(dev_priv)) {
error->gtier[0] = I915_READ(GTIER);
error->ier = I915_READ(VLV_IER);
error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
@@ -1400,7 +1400,7 @@ static void i915_capture_reg_state(struct 
drm_i915_private *dev_priv,
error->gtier[0] = I915_READ(GTIER);
} else if (IS_GEN2(dev)) {
error->ier = I915_READ16(IER);
-   } else if (!IS_VALLEYVIEW(dev)) {
+   } else if (!IS_VALLEYVIEW(dev_priv)) {
error->ier = I915_READ(IER);
}
error->eir = I915_READ(EIR);
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 023fd84f8f7b..df75a343e825 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -253,7 +253,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
 
if (HAS_PCH_LPT(dev_priv))
max_clock = 18;
-   else if (IS_VALLEYVIEW(dev))
+   else if (IS_VALLEYVIEW(dev_priv))
/*
 * 270 MHz due to current DPLL limits,
 * DAC limit supposedly 355 MHz.
@@ -423,7 +423,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector 
*connector)
if (HAS_PCH_SPLIT(dev_priv))
return intel_ironlake_crt_detect_hotplug(connector);
 
-   if (IS_VALLEYVIEW(dev))
+   if (IS_VALLEYVIEW(dev_priv))
return valleyview_crt_detect_hotplug(connector);
 
/*
@@ -850,7 +850,7 @@ void intel_crt_init(struct drm_device *dev)
 
if (HAS_PCH_SPLIT(dev_priv))
adpa_reg = PCH_ADPA;
-   else if (IS_VALLEYVIEW(dev))
+   else if (IS_VALLEYVIEW(dev_priv))
adpa_reg = VLV_ADPA;
else
adpa_reg = ADPA;
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 2356b3ca9705..0540afc3fef4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5873,7 +5873,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
dev_priv->max_cdclk_freq = 675000;
} else if (IS_CHERRYVIEW(dev_priv)) {
dev_priv->max_cdclk_freq = 32;
-   } else if (IS_VALLEYVIEW(dev)) {
+   } else if (IS_VALLEYVIEW(dev_priv)) {
dev_priv->max_cdclk_freq = 40;
} else 

[Intel-gfx] [PATCH 16/22] drm/i915: Make IS_BROXTON only take dev_priv

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Saves 1392 bytes of .rodata strings.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.c |  2 +-
 drivers/gpu/drm/i915/i915_drv.h |  5 +++--
 drivers/gpu/drm/i915/i915_gem_gtt.c | 40 +
 drivers/gpu/drm/i915/i915_irq.c |  2 +-
 drivers/gpu/drm/i915/intel_ddi.c|  4 ++--
 drivers/gpu/drm/i915/intel_display.c| 31 ++---
 drivers/gpu/drm/i915/intel_dp.c | 16 ++---
 drivers/gpu/drm/i915/intel_dpll_mgr.c   |  2 +-
 drivers/gpu/drm/i915/intel_dsi.c| 27 +++---
 drivers/gpu/drm/i915/intel_dsi_pll.c| 26 ++---
 drivers/gpu/drm/i915/intel_guc_loader.c |  8 +++
 drivers/gpu/drm/i915/intel_hdmi.c   |  6 ++---
 drivers/gpu/drm/i915/intel_runtime_pm.c |  2 +-
 13 files changed, 89 insertions(+), 82 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d854ea4a7e92..18af6d1ccec9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2437,7 +2437,7 @@ static int intel_runtime_resume(struct device *kdev)
if (IS_GEN6(dev_priv))
intel_init_pch_refclk(dev);
 
-   if (IS_BROXTON(dev)) {
+   if (IS_BROXTON(dev_priv)) {
bxt_disable_dc9(dev_priv);
bxt_display_core_init(dev_priv, true);
if (dev_priv->csr.dmc_payload &&
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0aeed1e31c17..3a5aac21f133 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2666,7 +2666,7 @@ struct drm_i915_cmd_table {
 #define IS_HASWELL(dev_priv)   (dev_priv->info.is_haswell)
 #define IS_BROADWELL(dev_priv) (dev_priv->info.is_broadwell)
 #define IS_SKYLAKE(dev_priv)   (dev_priv->info.is_skylake)
-#define IS_BROXTON(dev)(INTEL_INFO(dev)->is_broxton)
+#define IS_BROXTON(dev_priv)   (dev_priv->info.is_broxton)
 #define IS_KABYLAKE(dev_priv)  (dev_priv->info.is_kabylake)
 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
@@ -2726,7 +2726,8 @@ struct drm_i915_cmd_table {
 #define BXT_REVID_B0   0x3
 #define BXT_REVID_C0   0x9
 
-#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, 
until))
+#define IS_BXT_REVID(dev_priv, since, until) \
+   (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
 
 #define KBL_REVID_A0   0x0
 #define KBL_REVID_B0   0x1
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index cf43a5632961..e628691fe97e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -373,27 +373,29 @@ static void *kmap_page_dma(struct i915_page_dma *p)
 /* We use the flushing unmap only with ppgtt structures:
  * page directories, page tables and scratch pages.
  */
-static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
+static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr)
 {
/* There are only few exceptions for gen >=6. chv and bxt.
 * And we are not sure about the latter so play safe for now.
 */
-   if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
+   if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
drm_clflush_virt_range(vaddr, PAGE_SIZE);
 
kunmap_atomic(vaddr);
 }
 
 #define kmap_px(px) kmap_page_dma(px_base(px))
-#define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
+#define kunmap_px(ppgtt, vaddr) \
+   kunmap_page_dma(to_i915((ppgtt)->base.dev), (vaddr))
 
 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
-#define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
-#define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
+#define fill_px(dev_priv, px, v) fill_page_dma((dev_priv), px_base(px), (v))
+#define fill32_px(dev_priv, px, v) \
+   fill_page_dma_32((dev_priv), px_base(px), (v))
 
-static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
- const uint64_t val)
+static void fill_page_dma(struct drm_i915_private *dev_priv,
+ struct i915_page_dma *p, const uint64_t val)
 {
int i;
uint64_t * const vaddr = kmap_page_dma(p);
@@ -401,17 +403,17 @@ static void fill_page_dma(struct drm_device *dev, struct 
i915_page_dma *p,
for (i = 0; i < 512; i++)
vaddr[i] = val;
 
-   kunmap_page_dma(dev, vaddr);
+   kunmap_page_dma(dev_priv, vaddr);
 }
 
-static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
-const uint32_t val32)
+static void fill_page_dma_32(struct 

[Intel-gfx] [PATCH 17/22] drm/i915: Make HAS_L3_DPF only take dev_priv

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Saves 472 bytes of .rodata strings.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 drivers/gpu/drm/i915/i915_irq.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3a5aac21f133..38f1d7b8121c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2871,7 +2871,7 @@ struct drm_i915_cmd_table {
 #define HAS_GMCH_DISPLAY(dev_priv) (dev_priv->info.has_gmch_display)
 
 /* DPF == dynamic parity feature */
-#define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf)
+#define HAS_L3_DPF(dev_priv) (dev_priv->info.has_l3_dpf)
 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
 2 : HAS_L3_DPF(dev_priv))
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 75f4ba935ebc..079ba7cfc971 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3592,7 +3592,7 @@ static void gen5_gt_irq_postinstall(struct drm_device 
*dev)
pm_irqs = gt_irqs = 0;
 
dev_priv->gt_irq_mask = ~0;
-   if (HAS_L3_DPF(dev)) {
+   if (HAS_L3_DPF(dev_priv)) {
/* L3 parity interrupt is always unmasked. */
dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv);
gt_irqs |= GT_PARITY_ERROR(dev_priv);
-- 
2.7.4

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[Intel-gfx] [PATCH 10/22] drm/i915: Make INTEL_DEVID only take dev_priv

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Saves 4472 bytes of .rodata strings.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.c|  14 +++--
 drivers/gpu/drm/i915/i915_drv.h| 111 +
 drivers/gpu/drm/i915/i915_gem.c|  36 +--
 drivers/gpu/drm/i915/i915_gem_stolen.c |   6 +-
 drivers/gpu/drm/i915/i915_gem_tiling.c |   3 +-
 drivers/gpu/drm/i915/i915_irq.c|   2 +-
 drivers/gpu/drm/i915/intel_crt.c   |   4 +-
 drivers/gpu/drm/i915/intel_display.c   |  58 +
 drivers/gpu/drm/i915/intel_dp.c|   2 +-
 drivers/gpu/drm/i915/intel_hdmi.c  |   2 +-
 drivers/gpu/drm/i915/intel_i2c.c   |   5 +-
 drivers/gpu/drm/i915/intel_lvds.c  |   9 ++-
 drivers/gpu/drm/i915/intel_pm.c|  26 
 drivers/gpu/drm/i915/intel_sdvo.c  |  11 ++--
 drivers/gpu/drm/i915/intel_tv.c|   4 +-
 15 files changed, 151 insertions(+), 142 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index fbb4e2e0d124..bfdbbb745939 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -188,12 +188,14 @@ static void intel_detect_pch(struct drm_device *dev)
dev_priv->pch_type = PCH_LPT;
DRM_DEBUG_KMS("Found LynxPoint PCH\n");
WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
-   WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
+   WARN_ON(IS_HSW_ULT(dev_priv) ||
+   IS_BDW_ULT(dev_priv));
} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_LPT;
DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
-   WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
+   WARN_ON(!IS_HSW_ULT(dev_priv) &&
+   !IS_BDW_ULT(dev_priv));
} else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_SPT;
DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
@@ -422,7 +424,7 @@ intel_setup_mchbar(struct drm_device *dev)
 
dev_priv->mchbar_need_disable = false;
 
-   if (IS_I915G(dev) || IS_I915GM(dev)) {
+   if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
pci_read_config_dword(dev_priv->bridge_dev, DEVEN, );
enabled = !!(temp & DEVEN_MCHBAR_EN);
} else {
@@ -440,7 +442,7 @@ intel_setup_mchbar(struct drm_device *dev)
dev_priv->mchbar_need_disable = true;
 
/* Space is allocated or reserved, so enable it. */
-   if (IS_I915G(dev) || IS_I915GM(dev)) {
+   if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
   temp | DEVEN_MCHBAR_EN);
} else {
@@ -456,7 +458,7 @@ intel_teardown_mchbar(struct drm_device *dev)
int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 
if (dev_priv->mchbar_need_disable) {
-   if (IS_I915G(dev) || IS_I915GM(dev)) {
+   if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
u32 deven_val;
 
pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
@@ -1077,7 +1079,7 @@ static int i915_driver_init_hw(struct drm_i915_private 
*dev_priv)
 * be lost or delayed, but we use them anyways to avoid
 * stuck interrupts on some machines.
 */
-   if (!IS_I945G(dev) && !IS_I945GM(dev)) {
+   if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
if (pci_enable_msi(pdev) < 0)
DRM_DEBUG_DRIVER("can't enable MSI");
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 06320001f3a8..3996b01d874a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2607,7 +2607,8 @@ struct drm_i915_cmd_table {
 })
 #define INTEL_INFO(p)  (&__I915__(p)->info)
 #define INTEL_GEN(p)   (INTEL_INFO(p)->gen)
-#define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
+
+#define INTEL_DEVID(dev_priv)  (dev_priv->info.device_id)
 
 #define REVID_FOREVER  0xff
 #define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision)
@@ -2639,27 +2640,27 @@ struct drm_i915_cmd_table {
 #define IS_REVID(p, since, until) \
(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
 
-#define IS_I830(dev)   (INTEL_DEVID(dev) == 0x3577)
-#define IS_845G(dev)   (INTEL_DEVID(dev) == 0x2562)
+#define IS_I830(dev_priv)  (INTEL_DEVID(dev_priv) == 0x3577)
+#define IS_845G(dev_priv)  

[Intel-gfx] [PATCH 09/22] drm/i915: Make IS_GEN-range macro only take dev_priv

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Saves 944 bytes of .rodata strings.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 619bec953b0d..06320001f3a8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2628,7 +2628,7 @@ struct drm_i915_cmd_table {
__e = BITS_PER_LONG - 1; \
else \
__e = (e) - 1; \
-   !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \
+   !!(dev_priv->info.gen_mask & GENMASK((__e), (__s))); \
 })
 
 /*
-- 
2.7.4

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[Intel-gfx] [PATCH 07/22] drm/i915: Make HAS_RUNTIME_PM only take dev_priv

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Saves 960 bytes of .rodata strings.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.c | 4 ++--
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +--
 3 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 89d322215c84..fbb4e2e0d124 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2308,7 +2308,7 @@ static int intel_runtime_suspend(struct device *kdev)
if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(
return -ENODEV;
 
-   if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
+   if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
return -ENODEV;
 
DRM_DEBUG_KMS("Suspending device\n");
@@ -2412,7 +2412,7 @@ static int intel_runtime_resume(struct device *kdev)
struct drm_i915_private *dev_priv = to_i915(dev);
int ret = 0;
 
-   if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
+   if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
return -ENODEV;
 
DRM_DEBUG_KMS("Resuming device\n");
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b9c82974c824..619bec953b0d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2820,12 +2820,12 @@ struct drm_i915_cmd_table {
 #define HAS_DDI(dev_priv)  (dev_priv->info.has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev)(INTEL_INFO(dev)->has_fpga_dbg)
 #define HAS_PSR(dev)   (INTEL_INFO(dev)->has_psr)
-#define HAS_RUNTIME_PM(dev)(INTEL_INFO(dev)->has_runtime_pm)
 #define HAS_RC6(dev)   (INTEL_INFO(dev)->has_rc6)
 #define HAS_RC6p(dev)  (INTEL_INFO(dev)->has_rc6p)
 
 #define HAS_CSR(dev)   (INTEL_INFO(dev)->has_csr)
 
+#define HAS_RUNTIME_PM(dev_priv) (dev_priv->info.has_runtime_pm)
 /*
  * For now, anything with a GuC requires uCode loading, and then supports
  * command submission once loaded. But these are logically independent
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6c11168facd6..ed1faf14f777 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2758,7 +2758,6 @@ void intel_runtime_pm_put(struct drm_i915_private 
*dev_priv)
 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
 {
struct pci_dev *pdev = dev_priv->drm.pdev;
-   struct drm_device *dev = _priv->drm;
struct device *kdev = >dev;
 
pm_runtime_set_autosuspend_delay(kdev, 1); /* 10s */
@@ -2770,7 +2769,7 @@ void intel_runtime_pm_enable(struct drm_i915_private 
*dev_priv)
 * so the driver's own RPM reference tracking asserts also work on
 * platforms without RPM support.
 */
-   if (!HAS_RUNTIME_PM(dev)) {
+   if (!HAS_RUNTIME_PM(dev_priv)) {
pm_runtime_dont_use_autosuspend(kdev);
pm_runtime_get_sync(kdev);
} else {
-- 
2.7.4

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[Intel-gfx] [PATCH 11/22] drm/i915: Make IS_IVYBRIDGE only take dev_priv

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Saves 848 bytes of .rodata strings.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.c | 19 +++
 drivers/gpu/drm/i915/i915_drv.h |  2 +-
 drivers/gpu/drm/i915/i915_gem.c |  2 +-
 drivers/gpu/drm/i915/i915_gem_context.c |  2 +-
 drivers/gpu/drm/i915/intel_display.c| 12 ++--
 drivers/gpu/drm/i915/intel_pm.c | 13 +++--
 drivers/gpu/drm/i915/intel_sprite.c |  2 +-
 7 files changed, 28 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index bfdbbb745939..f6ba8f262238 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -114,7 +114,7 @@ static bool i915_error_injected(struct drm_i915_private 
*dev_priv)
  fmt, ##__VA_ARGS__)
 
 
-static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
+static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
 {
enum intel_pch ret = PCH_NOP;
 
@@ -125,16 +125,16 @@ static enum intel_pch intel_virt_detect_pch(struct 
drm_device *dev)
 * make an educated guess as to which PCH is really there.
 */
 
-   if (IS_GEN5(dev)) {
+   if (IS_GEN5(dev_priv)) {
ret = PCH_IBX;
DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
-   } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
+   } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
ret = PCH_CPT;
DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
-   } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
+   } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
ret = PCH_LPT;
DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
-   } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
+   } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
ret = PCH_SPT;
DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
}
@@ -178,12 +178,14 @@ static void intel_detect_pch(struct drm_device *dev)
} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found CougarPoint PCH\n");
-   WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
+   WARN_ON(!(IS_GEN6(dev_priv) ||
+   IS_IVYBRIDGE(dev_priv)));
} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
/* PantherPoint is CPT compatible */
dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found PantherPoint PCH\n");
-   WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
+   WARN_ON(!(IS_GEN6(dev_priv) ||
+   IS_IVYBRIDGE(dev_priv)));
} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_LPT;
DRM_DEBUG_KMS("Found LynxPoint PCH\n");
@@ -217,7 +219,8 @@ static void intel_detect_pch(struct drm_device *dev)
PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
pch->subsystem_device ==
PCI_SUBDEVICE_ID_QEMU)) {
-   dev_priv->pch_type = intel_virt_detect_pch(dev);
+   dev_priv->pch_type =
+   intel_virt_detect_pch(dev_priv);
} else
continue;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3996b01d874a..1319544f97c5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2657,7 +2657,7 @@ struct drm_i915_cmd_table {
 #define IS_PINEVIEW(dev)   (INTEL_INFO(dev)->is_pineview)
 #define IS_G33(dev)(INTEL_INFO(dev)->is_g33)
 #define IS_IRONLAKE_M(dev_priv)(INTEL_DEVID(dev_priv) == 0x0046)
-#define IS_IVYBRIDGE(dev)  (INTEL_INFO(dev)->is_ivybridge)
+#define IS_IVYBRIDGE(dev_priv) (dev_priv->info.is_ivybridge)
 #define IS_IVB_GT1(dev_priv)   (INTEL_DEVID(dev_priv) == 0x0156 || \
 INTEL_DEVID(dev_priv) == 0x0152 || \
 INTEL_DEVID(dev_priv) == 0x015a)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 16e20d4f8036..b650c9c7addc 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4360,7 +4360,7 @@ i915_gem_init_hw(struct drm_device *dev)
   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
 
if (HAS_PCH_NOP(dev_priv)) {
-   if 

[Intel-gfx] [PATCH 19/22] drm/i915: Make IS_CHERRYVIEW only take dev_priv

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Saves 864 bytes of .rodata strings and ~100 of .text.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.c |  2 +-
 drivers/gpu/drm/i915/i915_drv.h |  8 ++--
 drivers/gpu/drm/i915/i915_gem_gtt.c |  2 +-
 drivers/gpu/drm/i915/intel_audio.c  |  4 +-
 drivers/gpu/drm/i915/intel_color.c  |  2 +-
 drivers/gpu/drm/i915/intel_display.c| 67 +
 drivers/gpu/drm/i915/intel_dp.c | 55 ++-
 drivers/gpu/drm/i915/intel_dsi.c|  8 ++--
 drivers/gpu/drm/i915/intel_hdmi.c   | 10 ++---
 drivers/gpu/drm/i915/intel_i2c.c|  2 +-
 drivers/gpu/drm/i915/intel_pm.c |  4 +-
 drivers/gpu/drm/i915/intel_psr.c|  4 +-
 drivers/gpu/drm/i915/intel_runtime_pm.c |  2 +-
 drivers/gpu/drm/i915/intel_sprite.c | 10 +++--
 14 files changed, 93 insertions(+), 87 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 18af6d1ccec9..5e7b6a1cb2c8 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -424,7 +424,7 @@ intel_setup_mchbar(struct drm_device *dev)
u32 temp;
bool enabled;
 
-   if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+   if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return;
 
dev_priv->mchbar_need_disable = false;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2162690ca44d..99e504703edd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2662,7 +2662,7 @@ struct drm_i915_cmd_table {
 INTEL_DEVID(dev_priv) == 0x0152 || \
 INTEL_DEVID(dev_priv) == 0x015a)
 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
-#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
+#define IS_CHERRYVIEW(dev_priv)(dev_priv->info.is_cherryview)
 #define IS_HASWELL(dev_priv)   (dev_priv->info.is_haswell)
 #define IS_BROADWELL(dev_priv) (dev_priv->info.is_broadwell)
 #define IS_SKYLAKE(dev_priv)   (dev_priv->info.is_skylake)
@@ -3840,11 +3840,11 @@ __raw_write(64, q)
 #define INTEL_BROADCAST_RGB_FULL 1
 #define INTEL_BROADCAST_RGB_LIMITED 2
 
-static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
+static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
 {
-   if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+   if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return VLV_VGACNTRL;
-   else if (INTEL_INFO(dev)->gen >= 5)
+   else if (INTEL_GEN(dev_priv) >= 5)
return CPU_VGACNTRL;
else
return VGACNTRL;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index e628691fe97e..4211b9a4a918 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2133,7 +2133,7 @@ static void gtt_write_workarounds(struct drm_device *dev)
/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */
if (IS_BROADWELL(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
-   else if (IS_CHERRYVIEW(dev))
+   else if (IS_CHERRYVIEW(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
else if (IS_SKYLAKE(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
diff --git a/drivers/gpu/drm/i915/intel_audio.c 
b/drivers/gpu/drm/i915/intel_audio.c
index 13b726916f98..d1275cbd5905 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -428,8 +428,8 @@ static void ilk_audio_codec_enable(struct drm_connector 
*connector,
aud_config = IBX_AUD_CFG(pipe);
aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
-   } else if (IS_VALLEYVIEW(connector->dev) ||
-  IS_CHERRYVIEW(connector->dev)) {
+   } else if (IS_VALLEYVIEW(dev_priv) ||
+  IS_CHERRYVIEW(dev_priv)) {
hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
aud_config = VLV_AUD_CFG(pipe);
aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
diff --git a/drivers/gpu/drm/i915/intel_color.c 
b/drivers/gpu/drm/i915/intel_color.c
index da76a799411a..445108855275 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -534,7 +534,7 @@ void intel_color_init(struct drm_crtc *crtc)
 
drm_mode_crtc_set_gamma_size(crtc, 256);
 
-   if (IS_CHERRYVIEW(dev)) {
+   if (IS_CHERRYVIEW(dev_priv)) {
dev_priv->display.load_csc_matrix = cherryview_load_csc_matrix;
dev_priv->display.load_luts = cherryview_load_luts;
} else if (IS_HASWELL(dev_priv)) {
diff --git 

[Intel-gfx] [PATCH 12/22] drm/i915: Make IS_BROADWELL only take dev_priv

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Saves 1808 bytes of .rodata strings.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.c |  6 --
 drivers/gpu/drm/i915/i915_drv.h |  6 +++---
 drivers/gpu/drm/i915/i915_gem.c |  5 +++--
 drivers/gpu/drm/i915/i915_gem_gtt.c |  2 +-
 drivers/gpu/drm/i915/intel_color.c  |  4 ++--
 drivers/gpu/drm/i915/intel_display.c| 21 +++--
 drivers/gpu/drm/i915/intel_dp.c | 19 ++-
 drivers/gpu/drm/i915/intel_pm.c | 20 +++-
 drivers/gpu/drm/i915/intel_psr.c|  4 ++--
 drivers/gpu/drm/i915/intel_runtime_pm.c |  3 +--
 drivers/gpu/drm/i915/intel_sprite.c |  8 
 11 files changed, 52 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f6ba8f262238..8899835fffab 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -189,13 +189,15 @@ static void intel_detect_pch(struct drm_device *dev)
} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_LPT;
DRM_DEBUG_KMS("Found LynxPoint PCH\n");
-   WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
+   WARN_ON(!IS_HASWELL(dev_priv) &&
+   !IS_BROADWELL(dev_priv));
WARN_ON(IS_HSW_ULT(dev_priv) ||
IS_BDW_ULT(dev_priv));
} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_LPT;
DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
-   WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
+   WARN_ON(!IS_HASWELL(dev_priv) &&
+   !IS_BROADWELL(dev_priv));
WARN_ON(!IS_HSW_ULT(dev_priv) &&
!IS_BDW_ULT(dev_priv));
} else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1319544f97c5..b3cfeebec806 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2664,7 +2664,7 @@ struct drm_i915_cmd_table {
 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
 #define IS_HASWELL(dev)(INTEL_INFO(dev)->is_haswell)
-#define IS_BROADWELL(dev)  (INTEL_INFO(dev)->is_broadwell)
+#define IS_BROADWELL(dev_priv) (dev_priv->info.is_broadwell)
 #define IS_SKYLAKE(dev)(INTEL_INFO(dev)->is_skylake)
 #define IS_BROXTON(dev)(INTEL_INFO(dev)->is_broxton)
 #define IS_KABYLAKE(dev)   (INTEL_INFO(dev)->is_kabylake)
@@ -2771,8 +2771,8 @@ struct drm_i915_cmd_table {
 #define HAS_LLC(dev)   (INTEL_INFO(dev)->has_llc)
 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
 #define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
-#define HAS_WT(dev)((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
-HAS_EDRAM(dev))
+#define HAS_WT(dev_priv)   ((IS_HASWELL(dev_priv) || \
+IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
 #define HWS_NEEDS_PHYSICAL(dev)(INTEL_INFO(dev)->hws_needs_physical)
 
 #define HAS_HW_CONTEXTS(dev)   (INTEL_INFO(dev)->has_hw_contexts)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b650c9c7addc..506480942946 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3469,7 +3469,7 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, 
void *data,
level = I915_CACHE_LLC;
break;
case I915_CACHING_DISPLAY:
-   level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
+   level = HAS_WT(dev_priv) ? I915_CACHE_WT : I915_CACHE_NONE;
break;
default:
return -EINVAL;
@@ -3527,7 +3527,8 @@ i915_gem_object_pin_to_display_plane(struct 
drm_i915_gem_object *obj,
 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
 */
ret = i915_gem_object_set_cache_level(obj,
- HAS_WT(obj->base.dev) ? 
I915_CACHE_WT : I915_CACHE_NONE);
+ HAS_WT(to_i915(obj->base.dev)) ?
+ I915_CACHE_WT : I915_CACHE_NONE);
if (ret) {
vma = ERR_PTR(ret);
goto err_unpin_display;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0bb4232f66bc..0f8f073c589c 

[Intel-gfx] [PATCH 03/22] drm/i915: Shrink per-platform watermark configuration

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Use types of more appropriate size in struct
intel_watermark_params to save 512 bytes of .rodata.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/intel_drv.h | 10 +-
 drivers/gpu/drm/i915/intel_pm.c  |  4 ++--
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c52b1d3a7ba0..59a73f8ca7af 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -799,11 +799,11 @@ struct intel_plane {
 };
 
 struct intel_watermark_params {
-   unsigned long fifo_size;
-   unsigned long max_wm;
-   unsigned long default_wm;
-   unsigned long guard_size;
-   unsigned long cacheline_size;
+   u16 fifo_size;
+   u16 max_wm;
+   u8 default_wm;
+   u8 guard_size;
+   u8 cacheline_size;
 };
 
 struct cxsr_latency {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3b1f0b40ccb9..96d0c57c816c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -775,13 +775,13 @@ static bool g4x_check_srwm(struct drm_device *dev,
  display_wm, cursor_wm);
 
if (display_wm > display->max_wm) {
-   DRM_DEBUG_KMS("display watermark is too large(%d/%ld), 
disabling\n",
+   DRM_DEBUG_KMS("display watermark is too large(%d/%u), 
disabling\n",
  display_wm, display->max_wm);
return false;
}
 
if (cursor_wm > cursor->max_wm) {
-   DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), 
disabling\n",
+   DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), 
disabling\n",
  cursor_wm, cursor->max_wm);
return false;
}
-- 
2.7.4

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[Intel-gfx] [PATCH 15/22] drm/i915: Make IS_SKYLAKE only take dev_priv

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Saves 1016 bytes of .rodata strings and couple hundred of .text.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
 drivers/gpu/drm/i915/intel_guc_loader.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 94651674e442..0aeed1e31c17 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2665,7 +2665,7 @@ struct drm_i915_cmd_table {
 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
 #define IS_HASWELL(dev_priv)   (dev_priv->info.is_haswell)
 #define IS_BROADWELL(dev_priv) (dev_priv->info.is_broadwell)
-#define IS_SKYLAKE(dev)(INTEL_INFO(dev)->is_skylake)
+#define IS_SKYLAKE(dev_priv)   (dev_priv->info.is_skylake)
 #define IS_BROXTON(dev)(INTEL_INFO(dev)->is_broxton)
 #define IS_KABYLAKE(dev_priv)  (dev_priv->info.is_kabylake)
 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 3246d51c7b8e..cf43a5632961 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2133,7 +2133,7 @@ static void gtt_write_workarounds(struct drm_device *dev)
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
else if (IS_CHERRYVIEW(dev))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
-   else if (IS_SKYLAKE(dev))
+   else if (IS_SKYLAKE(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
else if (IS_BROXTON(dev))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 3c46605b58e7..182204373931 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -726,7 +726,7 @@ void intel_guc_init(struct drm_device *dev)
 
if (!HAS_GUC_UCODE(dev)) {
fw_path = NULL;
-   } else if (IS_SKYLAKE(dev)) {
+   } else if (IS_SKYLAKE(dev_priv)) {
fw_path = I915_SKL_GUC_UCODE;
guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
-- 
2.7.4

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[Intel-gfx] [PATCH 04/22] drm/i915: Make HAS_DDI and HAS_PCH_LPT_LP only take dev_priv

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

This saves 3248 bytes of .rodata strings.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.h   |  8 +++---
 drivers/gpu/drm/i915/intel_crt.c  | 10 +++
 drivers/gpu/drm/i915/intel_display.c  | 49 ++-
 drivers/gpu/drm/i915/intel_dp.c   | 16 ++--
 drivers/gpu/drm/i915/intel_dpll_mgr.c |  4 +--
 drivers/gpu/drm/i915/intel_hdmi.c | 10 +++
 drivers/gpu/drm/i915/intel_pm.c   |  4 +--
 drivers/gpu/drm/i915/intel_psr.c  |  8 +++---
 8 files changed, 56 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4613f031d127..61e0cf7374ed 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2817,7 +2817,7 @@ struct drm_i915_cmd_table {
 
 #define HAS_DP_MST(dev)(INTEL_INFO(dev)->has_dp_mst)
 
-#define HAS_DDI(dev)   (INTEL_INFO(dev)->has_ddi)
+#define HAS_DDI(dev_priv)  (dev_priv->info.has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev)(INTEL_INFO(dev)->has_fpga_dbg)
 #define HAS_PSR(dev)   (INTEL_INFO(dev)->has_psr)
 #define HAS_RUNTIME_PM(dev)(INTEL_INFO(dev)->has_runtime_pm)
@@ -2856,8 +2856,10 @@ struct drm_i915_cmd_table {
 #define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
-#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == 
INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
-#define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == 
INTEL_PCH_LPT_DEVICE_ID_TYPE)
+#define HAS_PCH_LPT_LP(dev_priv) \
+   (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
+#define HAS_PCH_LPT_H(dev_priv) \
+   (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 88ebbdde185a..227eaf270226 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -280,13 +280,13 @@ static bool intel_crt_compute_config(struct intel_encoder 
*encoder,
 struct intel_crtc_state *pipe_config,
 struct drm_connector_state *conn_state)
 {
-   struct drm_device *dev = encoder->base.dev;
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
-   if (HAS_PCH_SPLIT(dev))
+   if (HAS_PCH_SPLIT(dev_priv))
pipe_config->has_pch_encoder = true;
 
/* LPT FDI RX only supports 8bpc. */
-   if (HAS_PCH_LPT(dev)) {
+   if (HAS_PCH_LPT(dev_priv)) {
if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
DRM_DEBUG_KMS("LPT only supports 24bpp\n");
return false;
@@ -296,7 +296,7 @@ static bool intel_crt_compute_config(struct intel_encoder 
*encoder,
}
 
/* FDI must always be 2.7 GHz */
-   if (HAS_DDI(dev))
+   if (HAS_DDI(dev_priv))
pipe_config->port_clock = 135000 * 2;
 
return true;
@@ -916,7 +916,7 @@ void intel_crt_init(struct drm_device *dev)
crt->base.enable = intel_enable_crt;
if (I915_HAS_HOTPLUG(dev))
crt->base.hpd_pin = HPD_CRT;
-   if (HAS_DDI(dev)) {
+   if (HAS_DDI(dev_priv)) {
crt->base.port = PORT_E;
crt->base.get_config = hsw_crt_get_config;
crt->base.get_hw_state = intel_ddi_get_hw_state;
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index a366656bcec5..235df123ac50 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1187,19 +1187,17 @@ void assert_fdi_rx_pll(struct drm_i915_private 
*dev_priv,
onoff(state), onoff(cur_state));
 }
 
-void assert_panel_unlocked(struct drm_i915_private *dev_priv,
-  enum pipe pipe)
+void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
 {
-   struct drm_device *dev = _priv->drm;
i915_reg_t pp_reg;
u32 val;
enum pipe panel_pipe = PIPE_A;
bool locked = true;
 
-   if (WARN_ON(HAS_DDI(dev)))
+   if (WARN_ON(HAS_DDI(dev_priv)))
return;
 
-   if (HAS_PCH_SPLIT(dev)) {
+   if (HAS_PCH_SPLIT(dev_priv)) {
u32 port_sel;
 
pp_reg = PP_CONTROL(0);
@@ -1209,7 +1207,7 @@ void assert_panel_unlocked(struct drm_i915_private 
*dev_priv,
I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
panel_pipe = PIPE_B;
/* XXX: else fix for eDP */
-   } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+   } else if 

Re: [Intel-gfx] [PATCH v4 1/3] drm/prime: Pass the right module owner through to dma_buf_export()

[Petri Latvala]

For the series:

Reviewed-by: Petri Latvala 

On 10/05/2016 03:21 PM, Chris Wilson wrote:

dma_buf_export() adds a reference to the owning module to the dmabuf (to
prevent the driver from being unloaded whilst a third party still refers
to the dmabuf). However, drm_gem_prime_export() was passing its own
THIS_MODULE (i.e. drm.ko) rather than the driver. Extract the right
owner from the device->fops instead.

v2: Use C99 initializers to zero out unset elements of
dma_buf_export_info
v3: Extract the right module from dev->fops.

Testcase: igt/vgem_basic/unload
Reported-by: Petri Latvala 
Signed-off-by: Chris Wilson 
Cc: Petri Latvala 
Cc: Christian König 
Cc: sta...@vger.kernel.org
Tested-by: Petri Latvala 
---
  drivers/gpu/drm/drm_prime.c | 17 ++---
  include/drm/drmP.h  |  3 ++-
  2 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
index 57201d68cf61..80907b34d857 100644
--- a/drivers/gpu/drm/drm_prime.c
+++ b/drivers/gpu/drm/drm_prime.c
@@ -397,14 +397,17 @@ static const struct dma_buf_ops drm_gem_prime_dmabuf_ops 
=  {
   * using the PRIME helpers.
   */
  struct dma_buf *drm_gem_prime_export(struct drm_device *dev,
-struct drm_gem_object *obj, int flags)
+struct drm_gem_object *obj,
+int flags)
  {
-   DEFINE_DMA_BUF_EXPORT_INFO(exp_info);
-
-   exp_info.ops = _gem_prime_dmabuf_ops;
-   exp_info.size = obj->size;
-   exp_info.flags = flags;
-   exp_info.priv = obj;
+   struct dma_buf_export_info exp_info = {
+   .exp_name = KBUILD_MODNAME, /* white lie for debug */
+   .owner = dev->driver->fops->owner,
+   .ops = _gem_prime_dmabuf_ops,
+   .size = obj->size,
+   .flags = flags,
+   .priv = obj,
+   };
  
  	if (dev->driver->gem_prime_res_obj)

exp_info.resv = dev->driver->gem_prime_res_obj(obj);
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index 0e99669159c1..81fcd553edf7 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -1012,7 +1012,8 @@ static inline int drm_debugfs_remove_files(const struct 
drm_info_list *files,
  #endif
  
  extern struct dma_buf *drm_gem_prime_export(struct drm_device *dev,

-   struct drm_gem_object *obj, int flags);
+   struct drm_gem_object *obj,
+   int flags);
  extern int drm_gem_prime_handle_to_fd(struct drm_device *dev,
struct drm_file *file_priv, uint32_t handle, uint32_t flags,
int *prime_fd);


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Re: [Intel-gfx] xrandr fails after resume from hibernation in kernels 4.7.4 and 4.8.0

[Gaston Gonzalez]

On Wed, Oct 05, 2016 at 07:23:23AM +0200, Greg KH wrote:
> On Tue, Oct 04, 2016 at 08:43:03PM -0300, Gaston Gonzalez wrote:
> > Hi,
> > 
> > After hibernation I get the following error when I tried to connect to 
> > monitor
> > through hdmi:
> > 
> > $ xrandr --output LVDS1 --off  --output  HDMI1 --auto
> > xrandr: Configure crtc 1 failed
> > 
> > This does not happen in kernel in kernel v4.6.7 but do happen in kernels 
> > v4.7.4
> > and v4.8.0
> 
> Ah, can you use 'git bisect' to track down the offending patch?
> 
> Also, if you let the graphics driver authors know, they are probably the
> best ones to help out with this, not the "generic" stable mailing list.
> 
> thanks,
> 
> greg k-h

Ok, I'll bisect this between v4.6.7 and v4.7.4

Added intel-gfx@lists.freedesktop.org in CC.

regards,

Gaston

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Re: [Intel-gfx] [PATCH v3] drm/i915/bxt: Broxton decoupled MMIO

[Tvrtko Ursulin]

On 04/10/2016 16:46, Praveen Paneri wrote:

Decoupled MMIO is an alternative way to access forcewake domain
registers, which requires less cycles for a single read/write and
avoids frequent software forcewake.
This certainly gives advantage over the forcewake as this new
mechanism “decouples” CPU cycles and allow them to complete even
when GT is in a CPD (frequency change) or C6 state.

This can co-exist with forcewake and we will continue to use forcewake
as appropriate. E.g. 64-bit register writes to avoid writing 2 dwords
separately and land into funny situations.

v2:
- Moved platform check out of the function and got rid of duplicate
  functions to find out decoupled power domain (Chris)
- Added a check for forcewake already held and skipped decoupled
  access (Chris)
- Skipped writing 64 bit registers through decoupled MMIO (Chris)

v3:
- Improved commit message with more info on decoupled mmio (Tvrtko)
- Changed decoupled operation to enum and used u32 instead of
  uint_32 data type for register offset (Tvrtko)
- Moved HAS_DECOUPLED_MMIO to device info (Tvrtko)
- Added lookup table for converting fw_engine to pd_engine (Tvrtko)
- Improved __gen9_decoupled_read and __gen9_decoupled_write routines (Tvrtko)

Signed-off-by: Zhe Wang 
Signed-off-by: Praveen Paneri 
---
  drivers/gpu/drm/i915/i915_drv.h |  18 +-
  drivers/gpu/drm/i915/i915_pci.c |   1 +
  drivers/gpu/drm/i915/i915_reg.h |   7 +++
  drivers/gpu/drm/i915/intel_uncore.c | 113 
  4 files changed, 138 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f8c66ee..bfdd55a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -559,6 +559,18 @@ enum forcewake_domains {
  #define FW_REG_READ  (1)
  #define FW_REG_WRITE (2)
  
+enum decoupled_power_domains {

+   GEN9_DECOUPLED_PD_BLITTER = 0,
+   GEN9_DECOUPLED_PD_RENDER,
+   GEN9_DECOUPLED_PD_MEDIA,
+   GEN9_DECOUPLED_PD_ALL
+};
+
+enum decoupled_ops {
+   GEN9_DECOUPLED_OP_WRITE = 0,
+   GEN9_DECOUPLED_OP_READ
+};
+
  enum forcewake_domains
  intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
   i915_reg_t reg, unsigned int op);
@@ -690,7 +702,8 @@ struct intel_csr {
func(has_snoop) sep \
func(has_ddi) sep \
func(has_fpga_dbg) sep \
-   func(has_pooled_eu)
+   func(has_pooled_eu) sep \
+   func(has_decoupled_mmio)
  
  #define DEFINE_FLAG(name) u8 name:1

  #define SEP_SEMICOLON ;
@@ -2869,6 +2882,9 @@ struct drm_i915_cmd_table {
  #define GT_FREQUENCY_MULTIPLIER 50
  #define GEN9_FREQ_SCALER 3
  
+#define HAS_DECOUPLED_MMIO(dev) (INTEL_INFO(dev)->has_decoupled_mmio \

+   && IS_BXT_REVID(dev, BXT_REVID_C0, REVID_FOREVER))
+
  #include "i915_trace.h"
  
  static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 31e6edd..5c56c0c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -360,6 +360,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_hw_contexts = 1,
.has_logical_ring_contexts = 1,
.has_guc = 1,
+   .has_decoupled_mmio = 1,
.ddb_size = 512,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8d44cee..bf7b4c9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7398,6 +7398,13 @@ enum {
  #define  SKL_FUSE_PG1_DIST_STATUS  (1<<26)
  #define  SKL_FUSE_PG2_DIST_STATUS  (1<<25)
  
+/* Decoupled MMIO register pair for kernel driver */

+#define GEN9_DECOUPLED_REG0_DW0_MMIO(0xF00)
+#define GEN9_DECOUPLED_REG0_DW1_MMIO(0xF04)
+#define GEN9_DECOUPLED_DW1_GO  (1<<31)
+#define GEN9_DECOUPLED_PD_SHIFT28
+#define GEN9_DECOUPLED_OP_SHIFT24
+
  /* Per-pipe DDI Function Control */
  #define _TRANS_DDI_FUNC_CTL_A 0x60400
  #define _TRANS_DDI_FUNC_CTL_B 0x61400
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index e2b188d..0af602e 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -831,6 +831,72 @@ unclaimed_reg_debug(struct drm_i915_private *dev_priv,
__unclaimed_reg_debug(dev_priv, reg, read, before);
  }
  
+static const enum decoupled_power_domains fw2dpd_engine[] = {

+   GEN9_DECOUPLED_PD_RENDER,
+   GEN9_DECOUPLED_PD_BLITTER,
+   GEN9_DECOUPLED_PD_ALL,
+   GEN9_DECOUPLED_PD_MEDIA,
+   GEN9_DECOUPLED_PD_ALL,
+   GEN9_DECOUPLED_PD_ALL,
+   GEN9_DECOUPLED_PD_ALL
+};
+
+/*
+ * Decoupled MMIO access for only 1 

[Intel-gfx] [PATCH 14/22] drm/i915: Make IS_KABYLAKE only take dev_priv

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Saves 1320 bytes of .rodata strings.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.c | 10 +-
 drivers/gpu/drm/i915/i915_drv.h |  6 +++---
 drivers/gpu/drm/i915/i915_gem_stolen.c  |  2 +-
 drivers/gpu/drm/i915/intel_ddi.c| 16 
 drivers/gpu/drm/i915/intel_display.c| 10 +-
 drivers/gpu/drm/i915/intel_dpll_mgr.c   |  2 +-
 drivers/gpu/drm/i915/intel_guc_loader.c |  2 +-
 drivers/gpu/drm/i915/intel_runtime_pm.c |  2 +-
 8 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 8899835fffab..d854ea4a7e92 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -203,17 +203,17 @@ static void intel_detect_pch(struct drm_device *dev)
} else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_SPT;
DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
-   WARN_ON(!IS_SKYLAKE(dev) &&
-   !IS_KABYLAKE(dev));
+   WARN_ON(!IS_SKYLAKE(dev_priv) &&
+   !IS_KABYLAKE(dev_priv));
} else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_SPT;
DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
-   WARN_ON(!IS_SKYLAKE(dev) &&
-   !IS_KABYLAKE(dev));
+   WARN_ON(!IS_SKYLAKE(dev_priv) &&
+   !IS_KABYLAKE(dev_priv));
} else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_KBP;
DRM_DEBUG_KMS("Found KabyPoint PCH\n");
-   WARN_ON(!IS_KABYLAKE(dev));
+   WARN_ON(!IS_KABYLAKE(dev_priv));
} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
   (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
   ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c535358dc7fb..94651674e442 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2667,7 +2667,7 @@ struct drm_i915_cmd_table {
 #define IS_BROADWELL(dev_priv) (dev_priv->info.is_broadwell)
 #define IS_SKYLAKE(dev)(INTEL_INFO(dev)->is_skylake)
 #define IS_BROXTON(dev)(INTEL_INFO(dev)->is_broxton)
-#define IS_KABYLAKE(dev)   (INTEL_INFO(dev)->is_kabylake)
+#define IS_KABYLAKE(dev_priv)  (dev_priv->info.is_kabylake)
 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
@@ -2734,8 +2734,8 @@ struct drm_i915_cmd_table {
 #define KBL_REVID_D0   0x3
 #define KBL_REVID_E0   0x4
 
-#define IS_KBL_REVID(p, since, until) \
-   (IS_KABYLAKE(p) && IS_REVID(p, since, until))
+#define IS_KBL_REVID(dev_priv, since, until) \
+   (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
 
 /*
  * The genX designation typically refers to the render engine, so render
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c 
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index cbea6fb83ce5..3508120b8c90 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -456,7 +456,7 @@ int i915_gem_init_stolen(struct drm_device *dev)
break;
default:
if (IS_BROADWELL(dev_priv) ||
-   IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev))
+   IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
bdw_get_stolen_reserved(dev_priv, _base,
_size);
else
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index cd7128b89b4d..07164e250adf 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1020,13 +1020,13 @@ static void bxt_ddi_clock_get(struct intel_encoder 
*encoder,
 void intel_ddi_clock_get(struct intel_encoder *encoder,
 struct intel_crtc_state *pipe_config)
 {
-   struct drm_device *dev = encoder->base.dev;
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
-   if (INTEL_INFO(dev)->gen <= 8)
+   if (INTEL_GEN(dev_priv) <= 8)
hsw_ddi_clock_get(encoder, pipe_config);
-   else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
+   else if (IS_SKYLAKE(dev_priv) || 

[Intel-gfx] [PATCH 06/22] drm/i915: Make HAS_GMCH_DISPLAY only take dev_priv

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

More .rodata string saving by avoid __I915__ magic inside WARNs.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.h| 2 +-
 drivers/gpu/drm/i915/intel_color.c | 6 +++---
 drivers/gpu/drm/i915/intel_display.c   | 8 
 drivers/gpu/drm/i915/intel_dp.c| 2 +-
 drivers/gpu/drm/i915/intel_dsi.c   | 2 +-
 drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +-
 drivers/gpu/drm/i915/intel_hdmi.c  | 5 +++--
 7 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6abcfb89d760..b9c82974c824 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2865,7 +2865,7 @@ struct drm_i915_cmd_table {
 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
 
-#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->has_gmch_display)
+#define HAS_GMCH_DISPLAY(dev_priv) (dev_priv->info.has_gmch_display)
 
 /* DPF == dynamic parity feature */
 #define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf)
diff --git a/drivers/gpu/drm/i915/intel_color.c 
b/drivers/gpu/drm/i915/intel_color.c
index 95a72771eea6..5362c07932d3 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -273,7 +273,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
enum pipe pipe = intel_crtc->pipe;
int i;
 
-   if (HAS_GMCH_DISPLAY(dev)) {
+   if (HAS_GMCH_DISPLAY(dev_priv)) {
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
assert_dsi_pll_enabled(dev_priv);
else
@@ -288,7 +288,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
(drm_color_lut_extract(lut[i].green, 8) << 8) |
drm_color_lut_extract(lut[i].blue, 8);
 
-   if (HAS_GMCH_DISPLAY(dev))
+   if (HAS_GMCH_DISPLAY(dev_priv))
I915_WRITE(PALETTE(pipe, i), word);
else
I915_WRITE(LGC_PALETTE(pipe, i), word);
@@ -297,7 +297,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
for (i = 0; i < 256; i++) {
uint32_t word = (i << 16) | (i << 8) | i;
 
-   if (HAS_GMCH_DISPLAY(dev))
+   if (HAS_GMCH_DISPLAY(dev_priv))
I915_WRITE(PALETTE(pipe, i), word);
else
I915_WRITE(LGC_PALETTE(pipe, i), word);
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 7a05f17e7cd6..f32298af450c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5033,7 +5033,7 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
 * event which is after the vblank start event, so we need to have a
 * wait-for-vblank between disabling the plane and the pipe.
 */
-   if (HAS_GMCH_DISPLAY(dev)) {
+   if (HAS_GMCH_DISPLAY(dev_priv)) {
intel_set_memory_cxsr(dev_priv, false);
dev_priv->wm.vlv.cxsr = false;
intel_wait_for_vblank(dev, pipe);
@@ -5098,7 +5098,7 @@ static void intel_pre_plane_update(struct 
intel_crtc_state *old_crtc_state)
intel_pre_disable_primary(>base);
}
 
-   if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
+   if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) {
crtc->wm.cxsr_allowed = false;
 
/*
@@ -10892,7 +10892,7 @@ static void intel_crtc_update_cursor(struct drm_crtc 
*crtc,
pos |= y << CURSOR_Y_SHIFT;
 
/* ILK+ do this automagically */
-   if (HAS_GMCH_DISPLAY(dev) &&
+   if (HAS_GMCH_DISPLAY(dev_priv) &&
plane_state->base.rotation == DRM_ROTATE_180) {
base += (plane_state->base.crtc_h *
 plane_state->base.crtc_w - 1) * 4;
@@ -16590,7 +16590,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
if (crtc->active && !intel_crtc_has_encoders(crtc))
intel_crtc_disable_noatomic(>base);
 
-   if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
+   if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
/*
 * We start out with underrun reporting disabled to avoid races.
 * For correct bookkeeping mark this on active crtcs.
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0b6f1bab671d..51d92a9c6cb1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1583,7 +1583,7 @@ 

[Intel-gfx] [PATCH 05/22] drm/i915: Make INTEL_PCH_TYPE & co only take dev_priv

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

This saves 1872 bytes of .rodata strings.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.h   | 16 ++--
 drivers/gpu/drm/i915/i915_gem.c   |  2 +-
 drivers/gpu/drm/i915/i915_gpu_error.c |  4 +--
 drivers/gpu/drm/i915/i915_irq.c   | 20 +++
 drivers/gpu/drm/i915/intel_audio.c|  2 +-
 drivers/gpu/drm/i915/intel_crt.c  | 25 +-
 drivers/gpu/drm/i915/intel_display.c  | 48 ++-
 drivers/gpu/drm/i915/intel_dp.c   | 27 ++--
 drivers/gpu/drm/i915/intel_dpll_mgr.c |  2 +-
 drivers/gpu/drm/i915/intel_hdmi.c | 19 +++---
 drivers/gpu/drm/i915/intel_i2c.c  |  2 +-
 drivers/gpu/drm/i915/intel_lvds.c | 22 
 drivers/gpu/drm/i915/intel_pm.c   |  6 ++---
 drivers/gpu/drm/i915/intel_sdvo.c | 12 -
 14 files changed, 107 insertions(+), 100 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 61e0cf7374ed..6abcfb89d760 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2852,18 +2852,18 @@ struct drm_i915_cmd_table {
 #define INTEL_PCH_P3X_DEVICE_ID_TYPE   0x7000
 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE  0x2900 /* qemu q35 has 2918 */
 
-#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
-#define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
-#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
-#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
+#define INTEL_PCH_TYPE(dev_priv) (dev_priv->pch_type)
+#define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
+#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
+#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
 #define HAS_PCH_LPT_LP(dev_priv) \
(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
 #define HAS_PCH_LPT_H(dev_priv) \
(dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
-#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
-#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
-#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
-#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
+#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
+#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
+#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
+#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
 
 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->has_gmch_display)
 
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a89a88922448..520be605ca94 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4361,7 +4361,7 @@ i915_gem_init_hw(struct drm_device *dev)
I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
 
-   if (HAS_PCH_NOP(dev)) {
+   if (HAS_PCH_NOP(dev_priv)) {
if (IS_IVYBRIDGE(dev)) {
u32 temp = I915_READ(GEN7_MSG_CTL);
temp &= ~(WAIT_FOR_PCH_FLR_ACK | 
WAIT_FOR_PCH_RESET_ACK);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 8b85efbdfa04..6c7b0f0341b5 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -423,7 +423,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf 
*m,
for (i = 0; i < 4; i++)
err_printf(m, "GTIER gt %d: 0x%08x\n", i,
   error->gtier[i]);
-   } else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
+   } else if (HAS_PCH_SPLIT(dev_priv) || IS_VALLEYVIEW(dev_priv))
err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
@@ -1395,7 +1395,7 @@ static void i915_capture_reg_state(struct 
drm_i915_private *dev_priv,
error->ier = I915_READ(GEN8_DE_MISC_IER);
for (i = 0; i < 4; i++)
error->gtier[i] = I915_READ(GEN8_GT_IER(i));
-   } else if (HAS_PCH_SPLIT(dev)) {
+   } else if (HAS_PCH_SPLIT(dev_priv)) {
error->ier = I915_READ(DEIER);
error->gtier[0] = I915_READ(GTIER);
} else if (IS_GEN2(dev)) {
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index bd6c8b0eeaef..883474411aee 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3237,12 +3237,12 @@ static void ibx_irq_reset(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = to_i915(dev);
 
-   if (HAS_PCH_NOP(dev))
+   if (HAS_PCH_NOP(dev_priv))
return;
 
 

[Intel-gfx] [PATCH 13/22] drm/i915: Make IS_HASWELL only take dev_priv

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Saves 2432 bytes of .rodata strings.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.h  |  2 +-
 drivers/gpu/drm/i915/i915_gem.c  |  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c  |  4 ++--
 drivers/gpu/drm/i915/i915_irq.c  |  4 ++--
 drivers/gpu/drm/i915/i915_reg.h  |  4 ++--
 drivers/gpu/drm/i915/intel_color.c   |  4 ++--
 drivers/gpu/drm/i915/intel_ddi.c |  2 +-
 drivers/gpu/drm/i915/intel_display.c | 23 ++-
 drivers/gpu/drm/i915/intel_psr.c |  6 +++---
 9 files changed, 24 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b3cfeebec806..c535358dc7fb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2663,7 +2663,7 @@ struct drm_i915_cmd_table {
 INTEL_DEVID(dev_priv) == 0x015a)
 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
-#define IS_HASWELL(dev)(INTEL_INFO(dev)->is_haswell)
+#define IS_HASWELL(dev_priv)   (dev_priv->info.is_haswell)
 #define IS_BROADWELL(dev_priv) (dev_priv->info.is_broadwell)
 #define IS_SKYLAKE(dev)(INTEL_INFO(dev)->is_skylake)
 #define IS_BROXTON(dev)(INTEL_INFO(dev)->is_broxton)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 506480942946..f11a68189774 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4356,7 +4356,7 @@ i915_gem_init_hw(struct drm_device *dev)
if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9)
I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
 
-   if (IS_HASWELL(dev))
+   if (IS_HASWELL(dev_priv))
I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0f8f073c589c..3246d51c7b8e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1746,7 +1746,7 @@ static void gen7_ppgtt_enable(struct drm_device *dev)
I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 
ecochk = I915_READ(GAM_ECOCHK);
-   if (IS_HASWELL(dev)) {
+   if (IS_HASWELL(dev_priv)) {
ecochk |= ECOCHK_PPGTT_WB_HSW;
} else {
ecochk |= ECOCHK_PPGTT_LLC_IVB;
@@ -2058,7 +2058,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
ppgtt->base.pte_encode = ggtt->base.pte_encode;
if (intel_vgpu_active(dev_priv) || IS_GEN6(dev))
ppgtt->switch_mm = gen6_mm_switch;
-   else if (IS_HASWELL(dev))
+   else if (IS_HASWELL(dev_priv))
ppgtt->switch_mm = hsw_mm_switch;
else if (IS_GEN7(dev))
ppgtt->switch_mm = gen7_mm_switch;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5fb3b1c9a52c..47337aabc326 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3594,8 +3594,8 @@ static void gen5_gt_irq_postinstall(struct drm_device 
*dev)
dev_priv->gt_irq_mask = ~0;
if (HAS_L3_DPF(dev)) {
/* L3 parity interrupt is always unmasked. */
-   dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
-   gt_irqs |= GT_PARITY_ERROR(dev);
+   dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv);
+   gt_irqs |= GT_PARITY_ERROR(dev_priv);
}
 
gt_irqs |= GT_RENDER_USER_INTERRUPT;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index acc767a52d8e..8b61669af628 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2094,9 +2094,9 @@ enum skl_disp_power_wells {
 #define PM_VEBOX_CS_ERROR_INTERRUPT(1 << 12) /* hsw+ */
 #define PM_VEBOX_USER_INTERRUPT(1 << 10) /* hsw+ */
 
-#define GT_PARITY_ERROR(dev) \
+#define GT_PARITY_ERROR(dev_priv) \
(GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
-(IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
+(IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
 
 /* These are all the "old" interrupts */
 #define ILK_BSD_USER_INTERRUPT (1<<5)
diff --git a/drivers/gpu/drm/i915/intel_color.c 
b/drivers/gpu/drm/i915/intel_color.c
index be76ef88678c..da76a799411a 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -326,7 +326,7 @@ static void haswell_load_luts(struct drm_crtc_state 
*crtc_state)
 * Workaround : Do not read or write the pipe palette/gamma data while
 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
 */
-   if (IS_HASWELL(dev) && 

[Intel-gfx] [PATCH 00/22] .rodata diet

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Dynamic typing in __I915__ (INTEL_INFO) has and unfortuante consequence that
for every time it is called under a WARN it generates a very verbose string
placed into the appropriate .rodata section.

Each instance of that can can several hundred bytes to the binary. One example
of such strings found in the binary, not word-wrapped is:

WARN_ON(!((&({ struct drm_i915_private *__p; if 
(__builtin_types_compatible_p(typeof(*dev_priv), struct drm_i915_private)) __p 
= (struct drm_i915_private *)dev_priv; else if 
(__builtin_types_compatible_p(typeof(*dev_priv), struct drm_device)) __p = 
to_i915((struct drm_device *)dev_priv); else do { bool __cond = !(!(1)); extern 
void __compiletime_assert_1912(void) __attribute__((error("BUILD_BUG 
failed"))); if (__cond) __compiletime_assert_1912(); do { } while (0); } while 
(0); __p; })->info)->has_ddi) && (control & (0x << 16)) != (0xabcd << 16))

If we gradually remove dynamic typing abilities from individual macros we can
start bringing the size of the binary down.

For example after this series:

   textdata bss dec hex filename
1067727   23256 576 1091559  10a7e7 i915.ko.nightly
1038202   23256 576 1062034  103492 i915.ko.diet

Which is a ~29KiB saving.

This is disruptive of course, but perhaps it is time to bite the bullet since we
now have a situation that even new platforms like Kabylake are adding code which
uses the wrong thing in those macros (dev instead of dev_priv).

The way I have done it here makes it impossible to use the converted macros in
a wrong way going forward.

P.S. Series starts with three diffrent type of .rodata shrinkage patches. I was
just lazy to split that up.

Tvrtko Ursulin (22):
  drm/i915: Shrink cxsr_latency_table
  drm/i915: Shrink sdvo_cmd_names
  drm/i915: Shrink per-platform watermark configuration
  drm/i915: Make HAS_DDI and HAS_PCH_LPT_LP only take dev_priv
  drm/i915: Make INTEL_PCH_TYPE & co only take dev_priv
  drm/i915: Make HAS_GMCH_DISPLAY only take dev_priv
  drm/i915: Make HAS_RUNTIME_PM only take dev_priv
  drm/i915: Do not use INTEL_INFO(dev_priv)->ring_mask inside WARNs
  drm/i915: Make IS_GEN-range macro only take dev_priv
  drm/i915: Make INTEL_DEVID only take dev_priv
  drm/i915: Make IS_IVYBRIDGE only take dev_priv
  drm/i915: Make IS_BROADWELL only take dev_priv
  drm/i915: Make IS_HASWELL only take dev_priv
  drm/i915: Make IS_KABYLAKE only take dev_priv
  drm/i915: Make IS_SKYLAKE only take dev_priv
  drm/i915: Make IS_BROXTON only take dev_priv
  drm/i915: Make HAS_L3_DPF only take dev_priv
  drm/i915: Make IS_G4X only take dev_priv
  drm/i915: Make IS_CHERRYVIEW only take dev_priv
  drm/i915: Make IS_VALLEYVIEW only take dev_priv
  drm/i915: Make INTEL_GEN only take dev_priv
  drm/i915: Make IS_GEN macros only take dev_priv

 drivers/gpu/drm/i915/i915_debugfs.c  |   4 +-
 drivers/gpu/drm/i915/i915_drv.c  |  63 ++--
 drivers/gpu/drm/i915/i915_drv.h  | 198 ++---
 drivers/gpu/drm/i915/i915_gem.c  |  55 ++--
 drivers/gpu/drm/i915/i915_gem_context.c  |   2 +-
 drivers/gpu/drm/i915/i915_gem_execbuffer.c   |   4 +-
 drivers/gpu/drm/i915/i915_gem_fence.c|  11 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c  |  60 ++--
 drivers/gpu/drm/i915/i915_gem_render_state.c |   6 +-
 drivers/gpu/drm/i915/i915_gem_stolen.c   |  17 +-
 drivers/gpu/drm/i915/i915_gem_tiling.c   |   7 +-
 drivers/gpu/drm/i915/i915_gpu_error.c|  18 +-
 drivers/gpu/drm/i915/i915_irq.c  |  34 +--
 drivers/gpu/drm/i915/i915_reg.h  |   4 +-
 drivers/gpu/drm/i915/i915_suspend.c  |   8 +-
 drivers/gpu/drm/i915/intel_audio.c   |   6 +-
 drivers/gpu/drm/i915/intel_color.c   |  16 +-
 drivers/gpu/drm/i915/intel_crt.c |  53 ++--
 drivers/gpu/drm/i915/intel_ddi.c |  22 +-
 drivers/gpu/drm/i915/intel_display.c | 416 ++-
 drivers/gpu/drm/i915/intel_dp.c  | 165 +--
 drivers/gpu/drm/i915/intel_dpll_mgr.c|  10 +-
 drivers/gpu/drm/i915/intel_drv.h |  28 +-
 drivers/gpu/drm/i915/intel_dsi.c |  37 ++-
 drivers/gpu/drm/i915/intel_dsi_pll.c |  26 +-
 drivers/gpu/drm/i915/intel_engine_cs.c   |   7 +-
 drivers/gpu/drm/i915/intel_fifo_underrun.c   |   8 +-
 drivers/gpu/drm/i915/intel_guc_loader.c  |  15 +-
 drivers/gpu/drm/i915/intel_hdmi.c|  58 ++--
 drivers/gpu/drm/i915/intel_i2c.c |   9 +-
 drivers/gpu/drm/i915/intel_lvds.c|  29 +-
 drivers/gpu/drm/i915/intel_pm.c  | 166 +--
 drivers/gpu/drm/i915/intel_psr.c |  22 +-
 drivers/gpu/drm/i915/intel_runtime_pm.c  |  15 +-
 drivers/gpu/drm/i915/intel_sdvo.c|  25 +-
 drivers/gpu/drm/i915/intel_sprite.c  |  30 +-
 drivers/gpu/drm/i915/intel_tv.c  |   4 +-
 37 files changed, 851 insertions(+), 807 

[Intel-gfx] [PATCH 01/22] drm/i915: Shrink cxsr_latency_table

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

unsigned long is too wide - use smaller types in
struct cxsr_latency to save 800-something bytes of .rodata.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/intel_drv.h | 16 
 drivers/gpu/drm/i915/intel_pm.c  |  4 ++--
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f48e79ae2ac6..c52b1d3a7ba0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -807,14 +807,14 @@ struct intel_watermark_params {
 };
 
 struct cxsr_latency {
-   int is_desktop;
-   int is_ddr3;
-   unsigned long fsb_freq;
-   unsigned long mem_freq;
-   unsigned long display_sr;
-   unsigned long display_hpll_disable;
-   unsigned long cursor_sr;
-   unsigned long cursor_hpll_disable;
+   bool is_desktop : 1;
+   bool is_ddr3 : 1;
+   unsigned int fsb_freq;
+   unsigned int mem_freq;
+   unsigned int display_sr;
+   unsigned int display_hpll_disable;
+   unsigned int cursor_sr;
+   unsigned int cursor_hpll_disable;
 };
 
 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, 
base)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7f1748a1e614..3b1f0b40ccb9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -252,8 +252,8 @@ static const struct cxsr_latency cxsr_latency_table[] = {
{0, 1, 400, 800, 6042, 36042, 6584, 36584},/* DDR3-800 SC */
 };
 
-static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
-int is_ddr3,
+static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
+bool is_ddr3,
 int fsb,
 int mem)
 {
-- 
2.7.4

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Re: [Intel-gfx] [PATCH v3 3/3] drm/vgem: Keep a reference to the dmabuf when mmaped

[Chris Wilson]

On Wed, Oct 05, 2016 at 03:11:00PM +0200, Daniel Vetter wrote:
> On Fri, Sep 30, 2016 at 02:59:59PM +0100, Chris Wilson wrote:
> > In order to keep the dmabuf alive whilst the mmap is, we need to hold a
> > reference to the dmabuf and not the backing object. This is important as
> > the dmabuf not only keeps the object alive, but also the device so that
> > 
> > dmabuf = vgem_create_dmabuf();
> > ptr = mmap(... dmabuf ...);
> > close(dmabuf);
> > 
> > persists across module-unload as well as device closure.
> 
> I don't see where we grab the ref to the dma-buf here instead of the
> backing storage. And doesn't the exact same issue happen when you use dumb
> mmap? Or maybe I'm just a bit confused about what's going on here ...

The reference to the dmabuf is in vma->vm_file, which was used to keep
the module alive. So this might be overzealous, in that there shouldn't
be a way to get back from the shmemfs object to the module. However,
that does make me aware of a failure path we have in patches that do add
callbacks from shmemfs to the driver...

At least using the ptr after closing the module is ok. So this patch is
not required.
-Chris

-- 
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Re: [Intel-gfx] [PATCH 00/22] .rodata diet

[Tvrtko Ursulin]

On 05/10/2016 14:01, Jani Nikula wrote:


On Wed, 05 Oct 2016, Tvrtko Ursulin  wrote:

Dynamic typing in __I915__ (INTEL_INFO) has and unfortuante consequence that
for every time it is called under a WARN it generates a very verbose string
placed into the appropriate .rodata section.

AFAIK the idea all along was to use this "dynamic typing" for a
transition period. I'm in favor of moving towards only accepting
dev_priv. I'm a bit hesitant to make the change in one go, though.


Oh right, maybe polymorphism would have been a better term to use. I 
know that it was a temporary solution but did not realize until 
yesterday what unbearable log messages it produces for WARNs and the 
bloat it adds.


Anyway, there are several arguments to be made here.

First of all, it has probably been some months since the last time 
people tried this (maybe in a slightly different form) so one point is 
that there will probably never be a good time for this amount of churn. 
However you do it it is so sprinkled all over that it is probably true.


Secondly, this series does not go all the way. The issue of converting 
things alike INTEL_INFO(*)->gen to INTEL_GEN remains. It would be 
another good chunk of work on top of this. Only when that is done could 
the __I915__ magic go away (more or less).


Positive is that every patch in this series helps a bit by locking down 
a particular macro to dev_priv. This is since it seems we are not 
catching and stopping all the new code which does the wrong thing during 
review. So applying a sub part of this series is still a good step IMHO.


Regards,

Tvrtko







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[Intel-gfx] [PATCH v4 2/3] drm/prime: Take a ref on the drm_dev when exporting a dma_buf

[Chris Wilson]

dma_buf may live a long time, longer than the last direct user of the
driver. We already hold a reference to the owner module (that prevents
the object code from disappearing), but there is no reference to the
drm_dev - so the pointers to the driver backend themselves may vanish.

v2: Resist temptation to fix the bug in armada_gem.c not setting the
correct flags on the exported dma-buf (it should pass the flags through
and not be arbitrarily setting O_RDWR).

Use a common wrapper for exporting the dmabuf and acquiring the
reference to the drm_device.

Testcase: igt/vgem_basic/unload
Suggested-by: Daniel Vetter 
Signed-off-by: Chris Wilson 
Cc: Petri Latvala 
Cc: Daniel Vetter 
Cc: sta...@vger.kernel.org
Tested-by: Petri Latvala 
---
 drivers/gpu/drm/armada/armada_gem.c|  2 +-
 drivers/gpu/drm/drm_prime.c| 30 +-
 drivers/gpu/drm/i915/i915_gem_dmabuf.c |  2 +-
 drivers/gpu/drm/tegra/gem.c|  2 +-
 drivers/gpu/drm/udl/udl_dmabuf.c   |  2 +-
 include/drm/drmP.h |  4 
 6 files changed, 37 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/armada/armada_gem.c 
b/drivers/gpu/drm/armada/armada_gem.c
index cb8f0347b934..a5e428d27d2f 100644
--- a/drivers/gpu/drm/armada/armada_gem.c
+++ b/drivers/gpu/drm/armada/armada_gem.c
@@ -547,7 +547,7 @@ armada_gem_prime_export(struct drm_device *dev, struct 
drm_gem_object *obj,
exp_info.flags = O_RDWR;
exp_info.priv = obj;
 
-   return dma_buf_export(_info);
+   return drm_gem_dmabuf_export(dev, _info);
 }
 
 struct drm_gem_object *
diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
index 80907b34d857..875df8d719fb 100644
--- a/drivers/gpu/drm/drm_prime.c
+++ b/drivers/gpu/drm/drm_prime.c
@@ -284,18 +284,46 @@ static void drm_gem_unmap_dma_buf(struct 
dma_buf_attachment *attach,
 }
 
 /**
+ * drm_gem_dmabuf_export - dma_buf export implementation for GEM
+ * @dma_buf: buffer to be exported
+ *
+ * This wraps dma_buf_export() for use by generic GEM drivers that are using
+ * drm_gem_dmabuf_release(). In addition to calling dma_buf_export(), we take
+ * a reference to the drm_device which is released by drm_gem_dmabuf_release().
+ *
+ * Returns the new dmabuf.
+ */
+struct dma_buf *drm_gem_dmabuf_export(struct drm_device *dev,
+ struct dma_buf_export_info *exp_info)
+{
+   struct dma_buf *dma_buf;
+
+   dma_buf = dma_buf_export(exp_info);
+   if (!IS_ERR(dma_buf))
+   drm_dev_ref(dev);
+
+   return dma_buf;
+}
+EXPORT_SYMBOL(drm_gem_dmabuf_export);
+
+/**
  * drm_gem_dmabuf_release - dma_buf release implementation for GEM
  * @dma_buf: buffer to be released
  *
  * Generic release function for dma_bufs exported as PRIME buffers. GEM drivers
  * must use this in their dma_buf ops structure as the release callback.
+ * drm_gem_dmabuf_release() should be used in conjunction with
+ * drm_gem_dmabuf_export().
  */
 void drm_gem_dmabuf_release(struct dma_buf *dma_buf)
 {
struct drm_gem_object *obj = dma_buf->priv;
+   struct drm_device *dev = obj->dev;
 
/* drop the reference on the export fd holds */
drm_gem_object_unreference_unlocked(obj);
+
+   drm_dev_unref(dev);
 }
 EXPORT_SYMBOL(drm_gem_dmabuf_release);
 
@@ -412,7 +440,7 @@ struct dma_buf *drm_gem_prime_export(struct drm_device *dev,
if (dev->driver->gem_prime_res_obj)
exp_info.resv = dev->driver->gem_prime_res_obj(obj);
 
-   return dma_buf_export(_info);
+   return drm_gem_dmabuf_export(dev, _info);
 }
 EXPORT_SYMBOL(drm_gem_prime_export);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_dmabuf.c 
b/drivers/gpu/drm/i915/i915_gem_dmabuf.c
index 10265bb35604..97c9d68b45df 100644
--- a/drivers/gpu/drm/i915/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/i915_gem_dmabuf.c
@@ -283,7 +283,7 @@ struct dma_buf *i915_gem_prime_export(struct drm_device 
*dev,
return ERR_PTR(ret);
}
 
-   dma_buf = dma_buf_export(_info);
+   dma_buf = drm_gem_dmabuf_export(dev, _info);
if (IS_ERR(dma_buf))
return dma_buf;
 
diff --git a/drivers/gpu/drm/tegra/gem.c b/drivers/gpu/drm/tegra/gem.c
index aa60d9909ea2..95e622e31931 100644
--- a/drivers/gpu/drm/tegra/gem.c
+++ b/drivers/gpu/drm/tegra/gem.c
@@ -613,7 +613,7 @@ struct dma_buf *tegra_gem_prime_export(struct drm_device 
*drm,
exp_info.flags = flags;
exp_info.priv = gem;
 
-   return dma_buf_export(_info);
+   return drm_gem_dmabuf_export(drm, _info);
 }
 
 struct drm_gem_object *tegra_gem_prime_import(struct drm_device *drm,
diff --git a/drivers/gpu/drm/udl/udl_dmabuf.c b/drivers/gpu/drm/udl/udl_dmabuf.c
index e2243edd1ce3..ac90ffdb5912 100644
--- a/drivers/gpu/drm/udl/udl_dmabuf.c
+++ b/drivers/gpu/drm/udl/udl_dmabuf.c
@@ -209,7 

[Intel-gfx] [PATCH v4 1/3] drm/prime: Pass the right module owner through to dma_buf_export()

[Chris Wilson]

dma_buf_export() adds a reference to the owning module to the dmabuf (to
prevent the driver from being unloaded whilst a third party still refers
to the dmabuf). However, drm_gem_prime_export() was passing its own
THIS_MODULE (i.e. drm.ko) rather than the driver. Extract the right
owner from the device->fops instead.

v2: Use C99 initializers to zero out unset elements of
dma_buf_export_info
v3: Extract the right module from dev->fops.

Testcase: igt/vgem_basic/unload
Reported-by: Petri Latvala 
Signed-off-by: Chris Wilson 
Cc: Petri Latvala 
Cc: Christian König 
Cc: sta...@vger.kernel.org
Tested-by: Petri Latvala 
---
 drivers/gpu/drm/drm_prime.c | 17 ++---
 include/drm/drmP.h  |  3 ++-
 2 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
index 57201d68cf61..80907b34d857 100644
--- a/drivers/gpu/drm/drm_prime.c
+++ b/drivers/gpu/drm/drm_prime.c
@@ -397,14 +397,17 @@ static const struct dma_buf_ops drm_gem_prime_dmabuf_ops 
=  {
  * using the PRIME helpers.
  */
 struct dma_buf *drm_gem_prime_export(struct drm_device *dev,
-struct drm_gem_object *obj, int flags)
+struct drm_gem_object *obj,
+int flags)
 {
-   DEFINE_DMA_BUF_EXPORT_INFO(exp_info);
-
-   exp_info.ops = _gem_prime_dmabuf_ops;
-   exp_info.size = obj->size;
-   exp_info.flags = flags;
-   exp_info.priv = obj;
+   struct dma_buf_export_info exp_info = {
+   .exp_name = KBUILD_MODNAME, /* white lie for debug */
+   .owner = dev->driver->fops->owner,
+   .ops = _gem_prime_dmabuf_ops,
+   .size = obj->size,
+   .flags = flags,
+   .priv = obj,
+   };
 
if (dev->driver->gem_prime_res_obj)
exp_info.resv = dev->driver->gem_prime_res_obj(obj);
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index 0e99669159c1..81fcd553edf7 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -1012,7 +1012,8 @@ static inline int drm_debugfs_remove_files(const struct 
drm_info_list *files,
 #endif
 
 extern struct dma_buf *drm_gem_prime_export(struct drm_device *dev,
-   struct drm_gem_object *obj, int flags);
+   struct drm_gem_object *obj,
+   int flags);
 extern int drm_gem_prime_handle_to_fd(struct drm_device *dev,
struct drm_file *file_priv, uint32_t handle, uint32_t flags,
int *prime_fd);
-- 
2.9.3

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Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [v2,1/2] drm/i915: Reduce trickery in DEV_INFO_FOR_EACH_FLAG

[Joonas Lahtinen]

On ke, 2016-10-05 at 11:19 +, Patchwork wrote:
> Test kms_pipe_crc_basic:
> Subgroup nonblocking-crc-pipe-a:
> pass   -> DMESG-WARN (fi-skl-6700k)

[drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO 
underrun

Existing bug;

https://bugs.freedesktop.org/show_bug.cgi?id=94605

> Subgroup suspend-read-crc-pipe-b:
> pass   -> DMESG-WARN (fi-byt-j1900)

[  622.590631] [drm:intel_dp_aux_ch [i915]] *ERROR* dp_aux_ch not done status 
0x0005

Opened a new bug at;

https://bugs.freedesktop.org/show_bug.cgi?id=98095

So nothing related to the series, good to merge unless there's a direct
Nack. Jani?

Regards, Joonas
-- 
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Open Source Technology Center
Intel Corporation
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[Intel-gfx] [PATCH v4 3/3] drm/vgem: Keep a reference to the dmabuf when mmaped

[Chris Wilson]

In order to keep the dmabuf alive whilst the mmap is, we need to hold a
reference to the dmabuf and not the backing object. This is important as
the dmabuf not only keeps the object alive, but also the device so that

dmabuf = vgem_create_dmabuf();
ptr = mmap(... dmabuf ...);
close(dmabuf);

persists across module-unload as well as device closure.

Testcase: igt/vgem_basic/unload
Signed-off-by: Chris Wilson 
Cc: Petri Latvala 
---
 drivers/gpu/drm/vgem/vgem_drv.c | 17 +++--
 1 file changed, 3 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/vgem/vgem_drv.c b/drivers/gpu/drm/vgem/vgem_drv.c
index f36c14729b55..74a83e41efa9 100644
--- a/drivers/gpu/drm/vgem/vgem_drv.c
+++ b/drivers/gpu/drm/vgem/vgem_drv.c
@@ -198,7 +198,6 @@ static struct drm_ioctl_desc vgem_ioctls[] = {
 
 static int vgem_mmap(struct file *filp, struct vm_area_struct *vma)
 {
-   unsigned long flags = vma->vm_flags;
int ret;
 
ret = drm_gem_mmap(filp, vma);
@@ -208,7 +207,7 @@ static int vgem_mmap(struct file *filp, struct 
vm_area_struct *vma)
/* Keep the WC mmaping set by drm_gem_mmap() but our pages
 * are ordinary and not special.
 */
-   vma->vm_flags = flags | VM_DONTEXPAND | VM_DONTDUMP;
+   vma->vm_flags &= ~(VM_IO | VM_PFNMAP);
return 0;
 }
 
@@ -281,21 +280,11 @@ static int vgem_prime_mmap(struct drm_gem_object *obj,
 {
int ret;
 
-   if (obj->size < vma->vm_end - vma->vm_start)
-   return -EINVAL;
-
-   if (!obj->filp)
-   return -ENODEV;
-
-   ret = obj->filp->f_op->mmap(obj->filp, vma);
+   ret = drm_gem_mmap_obj(obj, obj->size, vma);
if (ret)
return ret;
 
-   fput(vma->vm_file);
-   vma->vm_file = get_file(obj->filp);
-   vma->vm_flags |= VM_DONTEXPAND | VM_DONTDUMP;
-   vma->vm_page_prot = 
pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
-
+   vma->vm_flags &= ~(VM_IO | VM_PFNMAP);
return 0;
 }
 
-- 
2.9.3

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[Intel-gfx] ✗ Fi.CI.BAT: warning for Broxton ddi phy refactoring

[Patchwork]

== Series Details ==

Series: Broxton ddi phy refactoring
URL   : https://patchwork.freedesktop.org/series/13320/
State : warning

== Summary ==

Series 13320v1 Broxton ddi phy refactoring
https://patchwork.freedesktop.org/api/1.0/series/13320/revisions/1/mbox/

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-byt-j1900)
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-byt-j1900)
Test kms_psr_sink_crc:
Subgroup psr_basic:
dmesg-warn -> PASS   (fi-skl-6700hq)

fi-bdw-5557u total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050 total:244  pass:202  dwarn:0   dfail:0   fail:0   skip:42 
fi-bxt-t5700 total:244  pass:214  dwarn:0   dfail:0   fail:0   skip:30 
fi-byt-j1900 total:244  pass:211  dwarn:1   dfail:0   fail:1   skip:31 
fi-byt-n2820 total:244  pass:208  dwarn:0   dfail:0   fail:1   skip:35 
fi-hsw-4770  total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-hsw-4770r total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ilk-650   total:244  pass:182  dwarn:0   dfail:0   fail:2   skip:60 
fi-ivb-3520m total:244  pass:219  dwarn:0   dfail:0   fail:0   skip:25 
fi-ivb-3770  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 
fi-kbl-7200u total:244  pass:220  dwarn:0   dfail:0   fail:0   skip:24 
fi-skl-6260u total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hqtotal:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-skl-6700k total:244  pass:219  dwarn:1   dfail:0   fail:0   skip:24 
fi-skl-6770hqtotal:244  pass:228  dwarn:1   dfail:0   fail:1   skip:14 
fi-snb-2520m total:244  pass:208  dwarn:0   dfail:0   fail:0   skip:36 
fi-snb-2600  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 

Results at /archive/results/CI_IGT_test/Patchwork_2628/

0ff41ae4e5f083e3abcc170c1dab648f28b3 drm-intel-nightly: 
2016y-10m-05d-09h-47m-15s UTC integration manifest
dae03a4 drm/i915: Address broxton phy registers based on phy and channel number
474f0a2 drm/i915: Add location of the Rcomp resistor to bxt_ddi_phy_info
12bf891 drm/i915: Create a struct to hold information about the broxton phys
13a64e5 drm/i915: Move broxton vswing sequence to intel_dpio_phy.c
76d4a1d drm/i915: Move DPIO phy documentation section to intel_dpio_phy.c
88e0e98 drm/i915: Move broxton phy code to intel_dpio_phy.c
3cbc17f drm/i915: Pass lane count to bxt_ddi_phy_calc_lane_optmin_mask()
158e044 drm/i915: Explicitly map broxton DPIO power wells to phys
a7ca7d0 drm/i915: Rename struct i915_power_well field data to id

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Re: [Intel-gfx] [Regression report] Weekly regression report WW40

[Jani Nikula]

On Mon, 03 Oct 2016, Jairo Miramontes 
 wrote:
> This week regressions

In the past we used "regression", "bisect_pending", and "bisected" in
the bugzilla "Keywords" field. Can we start using those again, please?

BR,
Jani.


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Re: [Intel-gfx] [PATCH v3 3/3] drm/vgem: Keep a reference to the dmabuf when mmaped

[Daniel Vetter]

On Fri, Sep 30, 2016 at 02:59:59PM +0100, Chris Wilson wrote:
> In order to keep the dmabuf alive whilst the mmap is, we need to hold a
> reference to the dmabuf and not the backing object. This is important as
> the dmabuf not only keeps the object alive, but also the device so that
> 
>   dmabuf = vgem_create_dmabuf();
>   ptr = mmap(... dmabuf ...);
>   close(dmabuf);
> 
> persists across module-unload as well as device closure.

I don't see where we grab the ref to the dma-buf here instead of the
backing storage. And doesn't the exact same issue happen when you use dumb
mmap? Or maybe I'm just a bit confused about what's going on here ...
-Daniel

> 
> Testcase: igt/vgem_basic/unload
> Signed-off-by: Chris Wilson 
> Cc: Petri Latvala 
> ---
>  drivers/gpu/drm/vgem/vgem_drv.c | 17 +++--
>  1 file changed, 3 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/vgem/vgem_drv.c b/drivers/gpu/drm/vgem/vgem_drv.c
> index f36c14729b55..74a83e41efa9 100644
> --- a/drivers/gpu/drm/vgem/vgem_drv.c
> +++ b/drivers/gpu/drm/vgem/vgem_drv.c
> @@ -198,7 +198,6 @@ static struct drm_ioctl_desc vgem_ioctls[] = {
>  
>  static int vgem_mmap(struct file *filp, struct vm_area_struct *vma)
>  {
> - unsigned long flags = vma->vm_flags;
>   int ret;
>  
>   ret = drm_gem_mmap(filp, vma);
> @@ -208,7 +207,7 @@ static int vgem_mmap(struct file *filp, struct 
> vm_area_struct *vma)
>   /* Keep the WC mmaping set by drm_gem_mmap() but our pages
>* are ordinary and not special.
>*/
> - vma->vm_flags = flags | VM_DONTEXPAND | VM_DONTDUMP;
> + vma->vm_flags &= ~(VM_IO | VM_PFNMAP);
>   return 0;
>  }
>  
> @@ -281,21 +280,11 @@ static int vgem_prime_mmap(struct drm_gem_object *obj,
>  {
>   int ret;
>  
> - if (obj->size < vma->vm_end - vma->vm_start)
> - return -EINVAL;
> -
> - if (!obj->filp)
> - return -ENODEV;
> -
> - ret = obj->filp->f_op->mmap(obj->filp, vma);
> + ret = drm_gem_mmap_obj(obj, obj->size, vma);
>   if (ret)
>   return ret;
>  
> - fput(vma->vm_file);
> - vma->vm_file = get_file(obj->filp);
> - vma->vm_flags |= VM_DONTEXPAND | VM_DONTDUMP;
> - vma->vm_page_prot = 
> pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
> -
> + vma->vm_flags &= ~(VM_IO | VM_PFNMAP);
>   return 0;
>  }
>  
> -- 
> 2.9.3
> 
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[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [v4,1/3] drm/prime: Pass the right module owner through to dma_buf_export()

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/3] drm/prime: Pass the right module owner 
through to dma_buf_export()
URL   : https://patchwork.freedesktop.org/series/13322/
State : warning

== Summary ==

Series 13322v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/13322/revisions/1/mbox/

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-byt-j1900)
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-byt-j1900)

fi-bdw-5557u total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050 total:244  pass:202  dwarn:0   dfail:0   fail:0   skip:42 
fi-bxt-t5700 total:244  pass:214  dwarn:0   dfail:0   fail:0   skip:30 
fi-byt-j1900 total:244  pass:211  dwarn:1   dfail:0   fail:1   skip:31 
fi-hsw-4770  total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-hsw-4770r total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ilk-650   total:244  pass:182  dwarn:0   dfail:0   fail:2   skip:60 
fi-ivb-3520m total:244  pass:219  dwarn:0   dfail:0   fail:0   skip:25 
fi-ivb-3770  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 
fi-kbl-7200u total:244  pass:220  dwarn:0   dfail:0   fail:0   skip:24 
fi-skl-6260u total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hqtotal:244  pass:221  dwarn:1   dfail:0   fail:0   skip:22 
fi-skl-6700k total:244  pass:219  dwarn:1   dfail:0   fail:0   skip:24 
fi-skl-6770hqtotal:244  pass:228  dwarn:1   dfail:0   fail:1   skip:14 
fi-snb-2520m total:244  pass:208  dwarn:0   dfail:0   fail:0   skip:36 
fi-snb-2600  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 

Results at /archive/results/CI_IGT_test/Patchwork_2629/

0ff41ae4e5f083e3abcc170c1dab648f28b3 drm-intel-nightly: 
2016y-10m-05d-09h-47m-15s UTC integration manifest
20b2b15 drm/vgem: Keep a reference to the dmabuf when mmaped
f9d62da drm/prime: Take a ref on the drm_dev when exporting a dma_buf
4006ef4 drm/prime: Pass the right module owner through to dma_buf_export()

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Re: [Intel-gfx] [PATCH] drm/i915: Don't try to handle GuC when GuC is not supported.

[Daniel Vetter]

On Thu, Sep 22, 2016 at 04:55:07PM +, Vivi, Rodrigo wrote:
> On Wed, 2016-09-21 at 18:00 -0300, Paulo Zanoni wrote:
> > Em Qua, 2016-09-21 às 11:22 -0700, Rodrigo Vivi escreveu:
> > > Avoid any kind of GuC handling if GuC is not supported
> > > on a giving platform.
> > > 
> > > Besides being useless handling, our driver needs
> > > to be smarter than the user trying to use an invalid paramenter.
> > 
> > So the problem is when a platform doesn't support guc and the user
> > passes i915.enable_guc_something=1, right?
> 
> 1 is not a problem actually since it means "use if available". There is
> not firmware and execution continues.
> 
> 2 is the problem because it means "use guc or fail if not available".
> But platforms that don't have guc can't fail. driver needs to be smarter
> than that.

Not sure it needs to be smarter than that really, since all these debug
options auto-taint the kernel if you touch them. As in: You get to keep
all the pieces.

We can still do some auto-cleanup of modoptions ofc if there's a good need
for them.
-Daniel

> 
> > 
> > > 
> > > Cc: Jani Nikula 
> > > Cc: Anusha Srivatsa 
> > > Cc: Christophe Prigent 
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97573
> > > Signed-off-by: Rodrigo Vivi 
> > > ---
> > >  drivers/gpu/drm/i915/intel_guc_loader.c | 7 +++
> > >  1 file changed, 7 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
> > > b/drivers/gpu/drm/i915/intel_guc_loader.c
> > > index 6fd39ef..da0f5ed 100644
> > > --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> > > +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> > > @@ -720,6 +720,13 @@ void intel_guc_init(struct drm_device *dev)
> > >   struct intel_guc_fw *guc_fw = _priv->guc.guc_fw;
> > >   const char *fw_path;
> > >  
> > > + if (!HAS_GUC(dev)) {
> > > + i915.enable_guc_loading = 0;
> > > + i915.enable_guc_submission = 0;
> > > + fw_path = NULL;
> > > + return;
> > > + }
> > 
> > Instead of this, how about we just patch the code below with:
> > 
> > if (!HAS_GUC(dev_priv)) {
> > i915.enable_guc_loading = 0;
> > i915.enable_guc_submission = 0;
> > } else {
> > /* A negative value means "use platform default" */
> > if (i915.enable_guc_loading < 0)
> > i915.enable_guc_loading = HAS_GUC_UCODE(dev_priv);
> > if (i915.enable_guc_submission < 0)
> > i915.enable_guc_submission = HAS_GUC_SCHED(dev_priv);
> > }
> 
> yeap, this works as well. I just went for the simplest option that
> minimized at most any interactions for platforms where GuC simply
> doesn't exist.
> 
> > 
> > Or we could even go with our current "design pattern" and create
> > intel_sanitize_guc_options().
> 
> This is indeed a very good idea.
> 
> > 
> > This way we'll be able to avoid adding a second failure code path,
> > since we already have one for platforms with guc but options disabled.
> > 
> > 
> > > +
> > >   /* A negative value means "use platform default" */
> > >   if (i915.enable_guc_loading < 0)
> > >   i915.enable_guc_loading = HAS_GUC_UCODE(dev);
> 
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Re: [Intel-gfx] [PATCH 1/3] Revert "Skip intel_crt_init for Dell XPS 8700"

[Daniel Vetter]

On Mon, Sep 26, 2016 at 12:20:44PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä 
> 
> This reverts commit 10b6ee4a87811a110cb01eaca01eb04da6801baf.
> 
> According to [1] Dell XPS8700 VBT says 'int_crt_support 0', so thanks
> to commit e4abb733bb72 ("drm/i915: Check VBT for CRT port presence on
> HSW/BDW") we no longer need to blacklist it based on DMI.
> 
> Looking through the bug report, SFUSE_STRAP based detection was
> apparently also tried and failed, but the VBT based one should still
> work just fine.
> 
> The commit says that the symptom was a frozen machine, but based on the
> bug report it doesn't look like the CRT detection was at least directly
> responsible for such a drastic outcome.
> 
> Cc: Giacomo Comes 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=73559
> References: 
> http://lists.freedesktop.org/archives/intel-gfx/2014-January/038178.html [1]
> Signed-off-by: Ville Syrjälä 

Seems all rather reasonable. On all 3 patches:

Reviewed-by: Daniel Vetter 

> ---
>  drivers/gpu/drm/i915/intel_crt.c | 8 
>  1 file changed, 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_crt.c 
> b/drivers/gpu/drm/i915/intel_crt.c
> index 88ebbdde185a..ba372c239d48 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -823,14 +823,6 @@ static const struct dmi_system_id intel_no_crt[] = {
>   DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
>   },
>   },
> - {
> - .callback = intel_no_crt_dmi_callback,
> - .ident = "DELL XPS 8700",
> - .matches = {
> - DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
> - DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"),
> - },
> - },
>   { }
>  };
>  
> -- 
> 2.7.4
> 
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Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [v2,1/2] drm/i915: Reduce trickery in DEV_INFO_FOR_EACH_FLAG

[Joonas Lahtinen]

On ke, 2016-10-05 at 15:22 +0300, Joonas Lahtinen wrote:
> So nothing related to the series, good to merge unless there's a
> direct
> Nack. Jani?

Not-Ncked on IRC, so merged, thanks for the review!

Regards, Joonas
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Re: [Intel-gfx] [PATCH v3 3/3] drm/vgem: Keep a reference to the dmabuf when mmaped

[Daniel Vetter]

On Wed, Oct 05, 2016 at 02:40:09PM +0100, Chris Wilson wrote:
> On Wed, Oct 05, 2016 at 03:11:00PM +0200, Daniel Vetter wrote:
> > On Fri, Sep 30, 2016 at 02:59:59PM +0100, Chris Wilson wrote:
> > > In order to keep the dmabuf alive whilst the mmap is, we need to hold a
> > > reference to the dmabuf and not the backing object. This is important as
> > > the dmabuf not only keeps the object alive, but also the device so that
> > > 
> > >   dmabuf = vgem_create_dmabuf();
> > >   ptr = mmap(... dmabuf ...);
> > >   close(dmabuf);
> > > 
> > > persists across module-unload as well as device closure.
> > 
> > I don't see where we grab the ref to the dma-buf here instead of the
> > backing storage. And doesn't the exact same issue happen when you use dumb
> > mmap? Or maybe I'm just a bit confused about what's going on here ...
> 
> The reference to the dmabuf is in vma->vm_file, which was used to keep
> the module alive. So this might be overzealous, in that there shouldn't
> be a way to get back from the shmemfs object to the module. However,
> that does make me aware of a failure path we have in patches that do add
> callbacks from shmemfs to the driver...
> 
> At least using the ptr after closing the module is ok. So this patch is
> not required.

I think if we entirely redirect the mmap to shmem, and not forget to also
update vm_file, the driver could get unloaded without ill effects. I'll
leave this one out for now, picked up 1&2 from v4 to -misc meanwhile.
-Daniel
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Re: [Intel-gfx] [PATCH 00/22] .rodata diet

[Chris Wilson]

On Wed, Oct 05, 2016 at 02:39:16PM +0100, Tvrtko Ursulin wrote:
> 
> On 05/10/2016 14:01, Jani Nikula wrote:
> 
> >On Wed, 05 Oct 2016, Tvrtko Ursulin  wrote:
> >>Dynamic typing in __I915__ (INTEL_INFO) has and unfortuante consequence that
> >>for every time it is called under a WARN it generates a very verbose string
> >>placed into the appropriate .rodata section.
> >AFAIK the idea all along was to use this "dynamic typing" for a
> >transition period. I'm in favor of moving towards only accepting
> >dev_priv. I'm a bit hesitant to make the change in one go, though.
> 
> Oh right, maybe polymorphism would have been a better term to use. I
> know that it was a temporary solution but did not realize until
> yesterday what unbearable log messages it produces for WARNs and the
> bloat it adds.
> 
> Anyway, there are several arguments to be made here.
> 
> First of all, it has probably been some months since the last time
> people tried this (maybe in a slightly different form) so one point
> is that there will probably never be a good time for this amount of
> churn. However you do it it is so sprinkled all over that it is
> probably true.

The challenge with such sweeping changes is coordination of the trees.
David's fell flat because patches against -nightly couldn't be applied
against dinq. So for those we really need a back-merge + application.
 
> Secondly, this series does not go all the way. The issue of
> converting things alike INTEL_INFO(*)->gen to INTEL_GEN remains. It
> would be another good chunk of work on top of this. Only when that
> is done could the __I915__ magic go away (more or less).
> 
> Positive is that every patch in this series helps a bit by locking
> down a particular macro to dev_priv. This is since it seems we are
> not catching and stopping all the new code which does the wrong
> thing during review. So applying a sub part of this series is still
> a good step IMHO.

Yes, it does look gentler, and the .rodata does expain where David was
seeing the huge gains from the conversion.
-Chris

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Re: [Intel-gfx] [PATCH 00/22] .rodata diet

[Jani Nikula]

On Wed, 05 Oct 2016, Tvrtko Ursulin  wrote:
> Dynamic typing in __I915__ (INTEL_INFO) has and unfortuante consequence that
> for every time it is called under a WARN it generates a very verbose string
> placed into the appropriate .rodata section.

AFAIK the idea all along was to use this "dynamic typing" for a
transition period. I'm in favor of moving towards only accepting
dev_priv. I'm a bit hesitant to make the change in one go, though.

BR,
Jani.

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Re: [Intel-gfx] [PATCH 08/22] drm/i915: Do not use INTEL_INFO(dev_priv)->ring_mask inside WARNs

[Joonas Lahtinen]

On ke, 2016-10-05 at 13:33 +0100, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin 
> 
> Saves 1520 bytes of .rodata strings.
> 

Reviewed-by: Joonas Lahtinen 

Regards, Joonas
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Re: [Intel-gfx] [PATCH 01/11] drm/amdgpu: Remove call to reservation_object_test_signaled_rcu before wait

[Sumit Semwal]

Hi Alex,

On 23 September 2016 at 18:24, Daniel Vetter  wrote:
> On Mon, Aug 29, 2016 at 08:08:24AM +0100, Chris Wilson wrote:
>> Since fence_wait_timeout_reservation_object_wait_timeout_rcu() with a
>> timeout of 0 becomes reservation_object_test_signaled_rcu(), we do not
>> need to handle such conversion in the caller. The only challenge are
>> those callers that wish to differentiate the error code between the
>> nonblocking busy check and potentially blocking wait.
>>
>> Signed-off-by: Chris Wilson 
>> Cc: Alex Deucher 
>> Cc: Christian König 
>
> Reviewed-by: Daniel Vetter 
>> ---
I couldn't find if its already applied to your tree, or your acked-by;
could you please let me know if it's there, or if you'd like me to
pick it up via drm-misc (and an Acked-by would be appreciated in the
latter case :) )

Best,
Sumit.
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Re: [Intel-gfx] [PATCH 04/11] drm/nouveau: Remove call to reservation_object_test_signaled_rcu before wait

[Sumit Semwal]

Hi Ben,

On 23 September 2016 at 18:25, Daniel Vetter  wrote:
> On Mon, Aug 29, 2016 at 08:08:27AM +0100, Chris Wilson wrote:
>> Since fence_wait_timeout_reservation_object_wait_timeout_rcu() with a
>> timeout of 0 becomes reservation_object_test_signaled_rcu(), we do not
>> need to handle such conversion in the caller. The only challenge are
>> those callers that wish to differentiate the error code between the
>> nonblocking busy check and potentially blocking wait.
>>
>> Signed-off-by: Chris Wilson 
>> Cc: Ben Skeggs 
>
> Reviewed-by: Daniel Vetter 
>
May I please know if this patch is already in your queue, or should I
take it through drm-misc (in which case an Acked-by would be highly
appreciated :) )


Best,
Sumit.
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Re: [Intel-gfx] [PATCH 03/22] drm/i915: Shrink per-platform watermark configuration

[Ville Syrjälä]

On Wed, Oct 05, 2016 at 01:33:30PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Use types of more appropriate size in struct
> intel_watermark_params to save 512 bytes of .rodata.
> 
> Signed-off-by: Tvrtko Ursulin 
> ---
>  drivers/gpu/drm/i915/intel_drv.h | 10 +-
>  drivers/gpu/drm/i915/intel_pm.c  |  4 ++--
>  2 files changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index c52b1d3a7ba0..59a73f8ca7af 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -799,11 +799,11 @@ struct intel_plane {
>  };
>  
>  struct intel_watermark_params {
> - unsigned long fifo_size;
> - unsigned long max_wm;
> - unsigned long default_wm;
> - unsigned long guard_size;
> - unsigned long cacheline_size;
> + u16 fifo_size;
> + u16 max_wm;
> + u8 default_wm;
> + u8 guard_size;
> + u8 cacheline_size;
>  };

This thing has been bugging me since forever. And yet I never sent out a
fix. We could probably shrink things furher by tossing out a bunch of
the data since it's not all that diverse. But this looks like a decent
first step.

The other thing that bugs me about these is the defines for the actual
values. Makes it just that much harder to figure out what the actual
values are. I'm pretty sure I have a branch or two where I kill the
defines but naturally I can't find it right now. I'm too lazy to
double check the values now with this indirection in place, but your
choice of types does look reasonable, so

Acked-by: Ville Syrjälä 

>  
>  struct cxsr_latency {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3b1f0b40ccb9..96d0c57c816c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -775,13 +775,13 @@ static bool g4x_check_srwm(struct drm_device *dev,
> display_wm, cursor_wm);
>  
>   if (display_wm > display->max_wm) {
> - DRM_DEBUG_KMS("display watermark is too large(%d/%ld), 
> disabling\n",
> + DRM_DEBUG_KMS("display watermark is too large(%d/%u), 
> disabling\n",
> display_wm, display->max_wm);
>   return false;
>   }
>  
>   if (cursor_wm > cursor->max_wm) {
> - DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), 
> disabling\n",
> + DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), 
> disabling\n",
> cursor_wm, cursor->max_wm);
>   return false;
>   }
> -- 
> 2.7.4
> 
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Re: [Intel-gfx] [PATCH 02/11] drm/etnaviv: Remove manual call to reservation_object_test_signaled_rcu before wait

[Sumit Semwal]

Hi Lucas,

On 23 September 2016 at 18:25, Daniel Vetter  wrote:
> On Mon, Aug 29, 2016 at 08:08:25AM +0100, Chris Wilson wrote:
>> Since fence_wait_timeout_reservation_object_wait_timeout_rcu() with a
>> timeout of 0 becomes reservation_object_test_signaled_rcu(), we do not
>> need to handle such conversion in the caller. The only challenge are
>> those callers that wish to differentiate the error code between the
>> nonblocking busy check and potentially blocking wait.
>>
>> Signed-off-by: Chris Wilson 
>> Cc: Lucas Stach 
>> Cc: Russell King 
>> Cc: Christian Gmeiner 
>
> Reviewed-by: Daniel Vetter 
>
Could you please let me know if this is in your tree already, or would
you like me to take it via drm-misc (in which case, an Acked-by would
be fabulous!)

Thanks and best,
Sumit.
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Re: [Intel-gfx] [PATCH 01/22] drm/i915: Shrink cxsr_latency_table

[Ville Syrjälä]

On Wed, Oct 05, 2016 at 01:33:28PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> unsigned long is too wide - use smaller types in
> struct cxsr_latency to save 800-something bytes of .rodata.
> 
> Signed-off-by: Tvrtko Ursulin 
> ---
>  drivers/gpu/drm/i915/intel_drv.h | 16 
>  drivers/gpu/drm/i915/intel_pm.c  |  4 ++--
>  2 files changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index f48e79ae2ac6..c52b1d3a7ba0 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -807,14 +807,14 @@ struct intel_watermark_params {
>  };
>  
>  struct cxsr_latency {
> - int is_desktop;
> - int is_ddr3;
> - unsigned long fsb_freq;
> - unsigned long mem_freq;
> - unsigned long display_sr;
> - unsigned long display_hpll_disable;
> - unsigned long cursor_sr;
> - unsigned long cursor_hpll_disable;
> + bool is_desktop : 1;
> + bool is_ddr3 : 1;
> + unsigned int fsb_freq;
> + unsigned int mem_freq;
> + unsigned int display_sr;
> + unsigned int display_hpll_disable;
> + unsigned int cursor_sr;
> + unsigned int cursor_hpll_disable;

Am I blind or would all of the values fit even in u16?

>  };
>  
>  #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, 
> base)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 7f1748a1e614..3b1f0b40ccb9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -252,8 +252,8 @@ static const struct cxsr_latency cxsr_latency_table[] = {
>   {0, 1, 400, 800, 6042, 36042, 6584, 36584},/* DDR3-800 SC */
>  };
>  
> -static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
> -  int is_ddr3,
> +static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
> +  bool is_ddr3,
>int fsb,
>int mem)
>  {
> -- 
> 2.7.4
> 
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Re: [Intel-gfx] [PATCH 05/11] drm/vmwgfx: Remove call to reservation_object_test_signaled_rcu before wait

[Sumit Semwal]

Hi Thomas, Sinclair,

On 23 September 2016 at 18:26, Daniel Vetter  wrote:
> On Mon, Aug 29, 2016 at 08:08:28AM +0100, Chris Wilson wrote:
>> Since fence_wait_timeout_reservation_object_wait_timeout_rcu() with a
>> timeout of 0 becomes reservation_object_test_signaled_rcu(), we do not
>> need to handle such conversion in the caller. The only challenge are
>> those callers that wish to differentiate the error code between the
>> nonblocking busy check and potentially blocking wait.
>>
>> Signed-off-by: Chris Wilson 
>> Cc: Sinclair Yeh 
>> Cc: Thomas Hellstrom 
>> Reviewed-by: Sinclair Yeh 
>
> Reviewed-by: Daniel Vetter 
>
Could you please let me know if this patch is already queued up at
your end, or should I just take it via drm-misc with Sinclair's r-b?

Thanks and Best,
Sumit.
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Re: [Intel-gfx] [PATCH 03/22] drm/i915: Shrink per-platform watermark configuration

[Tvrtko Ursulin]

On 05/10/2016 16:07, Joonas Lahtinen wrote:

On ke, 2016-10-05 at 13:33 +0100, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

Use types of more appropriate size in struct
intel_watermark_params to save 512 bytes of .rodata.

Signed-off-by: Tvrtko Ursulin 

The code does seem to use datatypes very sloppily. Where did you pick
up these?


I was just nosing around in .rodata and wondered why a huge table of 
zeros. :)


Regards,

Tvrtko

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Re: [Intel-gfx] [PATCH 03/22] drm/i915: Shrink per-platform watermark configuration

[Tvrtko Ursulin]

On 05/10/2016 17:50, Tvrtko Ursulin wrote:


On 05/10/2016 16:07, Joonas Lahtinen wrote:

On ke, 2016-10-05 at 13:33 +0100, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

Use types of more appropriate size in struct
intel_watermark_params to save 512 bytes of .rodata.

Signed-off-by: Tvrtko Ursulin 

The code does seem to use datatypes very sloppily. Where did you pick
up these?


I was just nosing around in .rodata and wondered why a huge table of 
zeros. :)




Oops no, that was the cxsr table which stood out so much. After I found 
that one I nosed around some more to see which ones look wasteful.


Regards,

Tvrtko


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Re: [Intel-gfx] [PATCH 05/11] drm/vmwgfx: Remove call to reservation_object_test_signaled_rcu before wait

[Sinclair Yeh]

Hi,

I'm preparing a fixes pull request, and I'll include this one if it
hasn't been applied by others already.

Sinclair


On Wed, Oct 05, 2016 at 09:41:22PM +0530, Sumit Semwal wrote:
> Hi Thomas, Sinclair,
> 
> On 23 September 2016 at 18:26, Daniel Vetter  wrote:
> > On Mon, Aug 29, 2016 at 08:08:28AM +0100, Chris Wilson wrote:
> >> Since fence_wait_timeout_reservation_object_wait_timeout_rcu() with a
> >> timeout of 0 becomes reservation_object_test_signaled_rcu(), we do not
> >> need to handle such conversion in the caller. The only challenge are
> >> those callers that wish to differentiate the error code between the
> >> nonblocking busy check and potentially blocking wait.
> >>
> >> Signed-off-by: Chris Wilson 
> >> Cc: Sinclair Yeh 
> >> Cc: Thomas Hellstrom 
> >> Reviewed-by: Sinclair Yeh 
> >
> > Reviewed-by: Daniel Vetter 
> >
> Could you please let me know if this patch is already queued up at
> your end, or should I just take it via drm-misc with Sinclair's r-b?
> 
> Thanks and Best,
> Sumit.
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[Intel-gfx] ✗ Fi.CI.BAT: warning for Start of skl watermark cleanup

[Patchwork]

== Series Details ==

Series: Start of skl watermark cleanup
URL   : https://patchwork.freedesktop.org/series/1/
State : warning

== Summary ==

Series 1v1 Start of skl watermark cleanup
https://patchwork.freedesktop.org/api/1.0/series/1/revisions/1/mbox/

Test gem_exec_flush:
Subgroup basic-wb-rw-before-default:
pass   -> DMESG-WARN (fi-skl-6770hq)
Test gem_exec_nop:
Subgroup basic-series:
pass   -> DMESG-WARN (fi-skl-6770hq)
Test gem_sync:
Subgroup basic-store-each:
pass   -> DMESG-WARN (fi-skl-6770hq)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS   (fi-byt-j1900)

fi-bdw-5557u total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050 total:244  pass:202  dwarn:0   dfail:0   fail:0   skip:42 
fi-byt-j1900 total:244  pass:211  dwarn:1   dfail:0   fail:1   skip:31 
fi-byt-n2820 total:244  pass:208  dwarn:0   dfail:0   fail:1   skip:35 
fi-hsw-4770  total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-hsw-4770r total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ilk-650   total:244  pass:182  dwarn:0   dfail:0   fail:2   skip:60 
fi-ivb-3520m total:244  pass:219  dwarn:0   dfail:0   fail:0   skip:25 
fi-ivb-3770  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 
fi-kbl-7200u total:244  pass:220  dwarn:0   dfail:0   fail:0   skip:24 
fi-skl-6260u total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hqtotal:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-skl-6700k total:244  pass:219  dwarn:1   dfail:0   fail:0   skip:24 
fi-skl-6770hqtotal:244  pass:225  dwarn:4   dfail:0   fail:1   skip:14 
fi-snb-2520m total:244  pass:208  dwarn:0   dfail:0   fail:0   skip:36 
fi-snb-2600  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 

Results at /archive/results/CI_IGT_test/Patchwork_2631/

2dff18acaa95a26b882a5f9910d7ded514f18415 drm-intel-nightly: 
2016y-10m-05d-13h-58m-08s UTC integration manifest
a3677c1 drm/i915/gen9: Add ddb changes to atomic debug output
2c60227 drm/i915/gen9: Get rid of redundant watermark values
3c82abf drm/i915/gen9: Make skl_wm_level per-plane
a9ce8a2 drm/i915: Add enable_sagv option
20de548 drm/i915/skl: Remove linetime from skl_wm_values
acddab7 drm/i915/skl: Move per-pipe ddb allocations into crtc states

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Re: [Intel-gfx] [PATCH 03/22] drm/i915: Shrink per-platform watermark configuration

[Joonas Lahtinen]

On ke, 2016-10-05 at 13:33 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Use types of more appropriate size in struct
> intel_watermark_params to save 512 bytes of .rodata.
> 
> Signed-off-by: Tvrtko Ursulin 

The code does seem to use datatypes very sloppily. Where did you pick
up these?

Regards, Joonas
-- 
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Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [Regression report] Weekly regression report WW40

[Argotti, Yann]

> 
> On Mon, 03 Oct 2016, Jairo Miramontes
>  wrote:
> > This week regressions
> 
> In the past we used "regression", "bisect_pending", and "bisected" in
> the bugzilla "Keywords" field. Can we start using those again, please?

I think this is a very good idea Jani. So we can start to scrub current 
regression (and then igt linked one) and update accordingly.
Yann

> 
> BR,
> Jani.
> 
> 
> --
> Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] [PATCH 4/6] drm/i915/gen9: Make skl_wm_level per-plane

[Lyude]

Having skl_wm_level contain all of the watermarks for each plane is
annoying since it prevents us from having any sort of object to
represent a single watermark level, something we take advantage of in
the next commit to cut down on all of the copy paste code in here.

Signed-off-by: Lyude 
Cc: Maarten Lankhorst 
Cc: Ville Syrjälä 
Cc: Matt Roper 
---
 drivers/gpu/drm/i915/i915_drv.h  |   6 +-
 drivers/gpu/drm/i915/intel_drv.h |   6 +-
 drivers/gpu/drm/i915/intel_pm.c  | 208 +--
 3 files changed, 100 insertions(+), 120 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d26e5999..0f97d43 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1648,9 +1648,9 @@ struct skl_wm_values {
 };
 
 struct skl_wm_level {
-   bool plane_en[I915_MAX_PLANES];
-   uint16_t plane_res_b[I915_MAX_PLANES];
-   uint8_t plane_res_l[I915_MAX_PLANES];
+   bool plane_en;
+   uint16_t plane_res_b;
+   uint8_t plane_res_l;
 };
 
 /*
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 35ba282..d684f4f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -468,9 +468,13 @@ struct intel_pipe_wm {
bool sprites_scaled;
 };
 
-struct skl_pipe_wm {
+struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level trans_wm;
+};
+
+struct skl_pipe_wm {
+   struct skl_plane_wm planes[I915_MAX_PLANES];
uint32_t linetime;
 };
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index af96888..250f12d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3668,67 +3668,52 @@ static int
 skl_compute_wm_level(const struct drm_i915_private *dev_priv,
 struct skl_ddb_allocation *ddb,
 struct intel_crtc_state *cstate,
+struct intel_plane *intel_plane,
 int level,
 struct skl_wm_level *result)
 {
struct drm_atomic_state *state = cstate->base.state;
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
-   struct drm_plane *plane;
-   struct intel_plane *intel_plane;
-   struct intel_plane_state *intel_pstate;
+   struct drm_plane *plane = _plane->base;
+   struct intel_plane_state *intel_pstate = NULL;
uint16_t ddb_blocks;
enum pipe pipe = intel_crtc->pipe;
int ret;
+   int i = skl_wm_plane_id(intel_plane);
+
+   if (state)
+   intel_pstate =
+   intel_atomic_get_existing_plane_state(state,
+ intel_plane);
 
/*
-* We'll only calculate watermarks for planes that are actually
-* enabled, so make sure all other planes are set as disabled.
+* Note: If we start supporting multiple pending atomic commits against
+* the same planes/CRTC's in the future, plane->state will no longer be
+* the correct pre-state to use for the calculations here and we'll
+* need to change where we get the 'unchanged' plane data from.
+*
+* For now this is fine because we only allow one queued commit against
+* a CRTC.  Even if the plane isn't modified by this transaction and we
+* don't have a plane lock, we still have the CRTC's lock, so we know
+* that no other transactions are racing with us to update it.
 */
-   memset(result, 0, sizeof(*result));
-
-   for_each_intel_plane_mask(_priv->drm,
- intel_plane,
- cstate->base.plane_mask) {
-   int i = skl_wm_plane_id(intel_plane);
-
-   plane = _plane->base;
-   intel_pstate = NULL;
-   if (state)
-   intel_pstate =
-   intel_atomic_get_existing_plane_state(state,
- 
intel_plane);
+   if (!intel_pstate)
+   intel_pstate = to_intel_plane_state(plane->state);
 
-   /*
-* Note: If we start supporting multiple pending atomic commits
-* against the same planes/CRTC's in the future, plane->state
-* will no longer be the correct pre-state to use for the
-* calculations here and we'll need to change where we get the
-* 'unchanged' plane data from.
-*
-* For now this is fine because we only allow one queued commit
-* against a CRTC.  Even if the plane isn't modified by this
-* transaction and we don't have a plane lock, we still have
-* the 

Re: [Intel-gfx] [PATCH 7/9] drm/i915: Create a struct to hold information about the broxton phys

[Imre Deak]

On ke, 2016-10-05 at 15:09 +0300, Ander Conselvan de Oliveira wrote:
> Information about which phy is dual channel is hardcoded in the phy init
> sequence. Split that to a separate struct so the init sequence is more
> generic.
> 
> Signed-off-by: Ander Conselvan de Oliveira 
> ---
>  drivers/gpu/drm/i915/i915_reg.h   |  9 +++--
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 63 
> +--
>  2 files changed, 60 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f6d29fb..d3802c6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1308,8 +1308,13 @@ enum skl_disp_power_wells {
>  #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC, \
>   _PORT_CL1CM_DW30_A)
>  
> -/* Defined for PHY0 only */
> -#define BXT_PORT_CL2CM_DW6_BC_MMIO(0x6C358)
> +/* The spec defines this only for BXT PHY0, but lets assume that this
> + * would exist for PHY1 too if it had a second channel.
> + */
> +#define _PORT_CL2CM_DW6_A0x162358
> +#define _PORT_CL2CM_DW6_BC   0x6C358
> +#define BXT_PORT_CL2CM_DW6(phy)  _BXT_PHY((phy), 
> _PORT_CL2CM_DW6_BC, \
> + _PORT_CL2CM_DW6_A)
>  #define   DW6_OLDO_DYN_PWR_DOWN_EN   (1 << 28)
>  
>  /* BXT PHY Ref registers */
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c 
> b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index 2a18724..66d750a 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -114,6 +114,49 @@
>   * -
>   */
>  
> +/**
> + * struct bxt_ddi_phy_info - Hold info for a broxton DDI phy
> + */
> +struct bxt_ddi_phy_info {
> + /**
> +  * @dual_channel: true if this phy has a second channel.
> +  */
> + bool dual_channel;
> +
> + /**
> +  * @channel: struct containing per channel information.
> +  */
> + struct {
> + /**
> +  * @port: which port maps to this channel.
> +  */
> + enum port port;
> + } channel[2];
> +};
> +
> +static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
> + [DPIO_PHY0] = {
> + .dual_channel = true,
> +
> + .channel = {
> + [DPIO_CH0] = { .port = PORT_B },
> + [DPIO_CH1] = { .port = PORT_C },
> + }
> + },
> + [DPIO_PHY1] = {
> + .dual_channel = false,
> +
> + .channel = {
> + [DPIO_CH0] = { .port = PORT_A },
> + }
> + },
> +};
> +
> +{

Missing part above, got mangled into the next patch.

> + return (phy_info->dual_channel * BIT(phy_info->channel[DPIO_CH1].port)) 
> |
> + BIT(phy_info->channel[DPIO_CH0].port);
> +}
> +
>  void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
>     enum port port, u32 margin, u32 scale,
>     u32 enable, u32 deemphasis)
> @@ -183,9 +226,7 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private 
> *dev_priv,
>   return false;
>   }
>  
> - for_each_port_masked(port,
> -  phy == DPIO_PHY0 ? BIT(PORT_B) | BIT(PORT_C) :
> - BIT(PORT_A)) {
> + for_each_port_masked(port, bxt_phy_port_mask(phy_info)) {
>   u32 tmp = I915_READ(BXT_PHY_CTL(port));
>  
>   if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
> @@ -220,6 +261,7 @@ static void bxt_phy_wait_grc_done(struct drm_i915_private 
> *dev_priv,
>  
>  void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
>  {
> + const struct bxt_ddi_phy_info *phy_info = _ddi_phy_info[phy];
>   u32 val;
>  
>   if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
> @@ -272,10 +314,10 @@ void bxt_ddi_phy_init(struct drm_i915_private 
> *dev_priv, enum dpio_phy phy)
>   SUS_CLK_CONFIG;
>   I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
>  
> - if (phy == DPIO_PHY0) {
> - val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
> + if (phy_info->dual_channel) {
> + val = I915_READ(BXT_PORT_CL2CM_DW6(phy));
>   val |= DW6_OLDO_DYN_PWR_DOWN_EN;
> - I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
> + I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val);
>   }
>  
>   val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
> @@ -290,7 +332,7 @@ void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, 
> enum dpio_phy phy)
>    * FIXME: Clarify programming of the following, the register is
>    * read-only with bit 6 fixed at 0 at least in stepping A.
>    */
> - if (phy == DPIO_PHY1)
> + if (!phy_info->dual_channel)
>   val |= OCL2_LDOFUSE_PWR_DIS;
>   I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
>  
> @@ -363,6 

Re: [Intel-gfx] [PATCH 8/9] drm/i915: Add location of the Rcomp resistor to bxt_ddi_phy_info

[Imre Deak]

On ke, 2016-10-05 at 15:09 +0300, Ander Conselvan de Oliveira wrote:
> Use struct bxt_ddi_phy_info to hold information of where the Rcomp
> resistor is located, instead of hard coding it in the init sequence.
> 
> Note that this moves the enabling of the phy with the Rcomp resistor out
> of the power well enable code. That should be safe since
> bxt_ddi_phy_init() is called while the power domains lock is held, and
> that is the only way that function gets called, so there is no
> possibility of a concurrent phy enable caused by a power domain get
> call.
> 
> Signed-off-by: Ander Conselvan de Oliveira 
> ---
>  drivers/gpu/drm/i915/intel_dpio_phy.c   | 76 
> +
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 15 ---
>  2 files changed, 59 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c 
> b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index 66d750a..e8a75fd 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -124,6 +124,13 @@ struct bxt_ddi_phy_info {
>   bool dual_channel;
>  
>   /**
> +  * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor.
> +  * Otherwise the GRC value will be copied from the phy indicated by
> +  * this field.
> +  */
> + enum dpio_phy rcomp_phy;
> +
> + /**
>    * @channel: struct containing per channel information.
>    */
>   struct {
> @@ -137,6 +144,7 @@ struct bxt_ddi_phy_info {
>  static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
>   [DPIO_PHY0] = {
>   .dual_channel = true,
> + .rcomp_phy = DPIO_PHY1,
>  
>   .channel = {
>   [DPIO_CH0] = { .port = PORT_B },
> @@ -145,6 +153,7 @@ static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = 
> {
>   },
>   [DPIO_PHY1] = {
>   .dual_channel = false,
> + .rcomp_phy = -1,
>  
>   .channel = {
>   [DPIO_CH0] = { .port = PORT_A },
> @@ -152,6 +161,7 @@ static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = 
> {
>   },
>  };
>  
> +static u32 bxt_phy_port_mask(const struct bxt_ddi_phy_info *phy_info)
>  {
>   return (phy_info->dual_channel * BIT(phy_info->channel[DPIO_CH1].port)) 
> |
>   BIT(phy_info->channel[DPIO_CH0].port);
> @@ -199,6 +209,7 @@ void bxt_ddi_phy_set_signal_level(struct drm_i915_private 
> *dev_priv,
>  bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
>   enum dpio_phy phy)
>  {
> + const struct bxt_ddi_phy_info *phy_info = _ddi_phy_info[phy];
>   enum port port;
>  
>   if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
> @@ -212,9 +223,10 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private 
> *dev_priv,
>   return false;
>   }
>  
> - if (phy == DPIO_PHY1 &&
> - !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE)) {
> - DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't done\n");
> + if (phy_info->rcomp_phy == -1 &&
> + !(I915_READ(BXT_PORT_REF_DW3(phy)) & GRC_DONE)) {
> + DRM_DEBUG_DRIVER("DDI PHY %d powered, but GRC isn't done\n",
> +  phy);
>  
>   return false;
>   }
> @@ -259,14 +271,15 @@ static void bxt_phy_wait_grc_done(struct 
> drm_i915_private *dev_priv,
>   DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
>  }
>  
> -void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
> +static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
> +   enum dpio_phy phy)
>  {
>   const struct bxt_ddi_phy_info *phy_info = _ddi_phy_info[phy];
>   u32 val;
>  
>   if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
>   /* Still read out the GRC value for state verification */
> - if (phy == DPIO_PHY0)
> + if (phy_info->rcomp_phy != -1)
>   dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
>  
>   if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
> @@ -336,30 +349,32 @@ void bxt_ddi_phy_init(struct drm_i915_private 
> *dev_priv, enum dpio_phy phy)
>   val |= OCL2_LDOFUSE_PWR_DIS;
>   I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
>  
> - if (phy == DPIO_PHY0) {
> + if (phy_info->rcomp_phy != -1) {
>   uint32_t grc_code;
>   /*
>    * PHY0 isn't connected to an RCOMP resistor so copy over
>    * the corresponding calibrated value from PHY1, and disable
>    * the automatic calibration on PHY0.
>    */
> - val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, DPIO_PHY1);
> + val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv,
> +   phy_info->rcomp_phy);
>   grc_code = val << GRC_CODE_FAST_SHIFT |
>  

[Intel-gfx] ✗ Fi.CI.BAT: warning for .rodata diet

[Patchwork]

== Series Details ==

Series: .rodata diet
URL   : https://patchwork.freedesktop.org/series/13323/
State : warning

== Summary ==

Series 13323v1 .rodata diet
https://patchwork.freedesktop.org/api/1.0/series/13323/revisions/1/mbox/

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-byt-j1900)
Test pm_rpm:
Subgroup basic-pci-d3-state:
pass   -> DMESG-WARN (fi-skl-6700k)

fi-bdw-5557u total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050 total:244  pass:202  dwarn:0   dfail:0   fail:0   skip:42 
fi-bxt-t5700 total:244  pass:214  dwarn:0   dfail:0   fail:0   skip:30 
fi-byt-j1900 total:244  pass:211  dwarn:1   dfail:0   fail:1   skip:31 
fi-byt-n2820 total:244  pass:208  dwarn:0   dfail:0   fail:1   skip:35 
fi-hsw-4770  total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-hsw-4770r total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ilk-650   total:244  pass:182  dwarn:0   dfail:0   fail:2   skip:60 
fi-ivb-3520m total:244  pass:219  dwarn:0   dfail:0   fail:0   skip:25 
fi-ivb-3770  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 
fi-kbl-7200u total:244  pass:220  dwarn:0   dfail:0   fail:0   skip:24 
fi-skl-6260u total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hqtotal:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-skl-6700k total:244  pass:218  dwarn:2   dfail:0   fail:0   skip:24 
fi-skl-6770hqtotal:244  pass:228  dwarn:1   dfail:0   fail:1   skip:14 
fi-snb-2520m total:244  pass:208  dwarn:0   dfail:0   fail:0   skip:36 
fi-snb-2600  total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 

Results at /archive/results/CI_IGT_test/Patchwork_2630/

2dff18acaa95a26b882a5f9910d7ded514f18415 drm-intel-nightly: 
2016y-10m-05d-13h-58m-08s UTC integration manifest
00ccf0a drm/i915: Make IS_GEN macros only take dev_priv
4da6900 drm/i915: Make INTEL_GEN only take dev_priv
03c6fd6 drm/i915: Make IS_VALLEYVIEW only take dev_priv
9135264 drm/i915: Make IS_CHERRYVIEW only take dev_priv
683a19e drm/i915: Make IS_G4X only take dev_priv
e67c99f drm/i915: Make HAS_L3_DPF only take dev_priv
dc7f830 drm/i915: Make IS_BROXTON only take dev_priv
08810b7 drm/i915: Make IS_SKYLAKE only take dev_priv
25ce651 drm/i915: Make IS_KABYLAKE only take dev_priv
856ee48 drm/i915: Make IS_HASWELL only take dev_priv
1e7da6b drm/i915: Make IS_BROADWELL only take dev_priv
5086f9c drm/i915: Make IS_IVYBRIDGE only take dev_priv
2f34959 drm/i915: Make INTEL_DEVID only take dev_priv
a96c4e6 drm/i915: Make IS_GEN-range macro only take dev_priv
23fb855 drm/i915: Do not use INTEL_INFO(dev_priv)->ring_mask inside WARNs
ff5a7ed drm/i915: Make HAS_RUNTIME_PM only take dev_priv
7022abf drm/i915: Make HAS_GMCH_DISPLAY only take dev_priv
fcc11aa drm/i915: Make INTEL_PCH_TYPE & co only take dev_priv
6cb4531 drm/i915: Make HAS_DDI and HAS_PCH_LPT_LP only take dev_priv
3da6313 drm/i915: Shrink per-platform watermark configuration
9ac1a7d drm/i915: Shrink sdvo_cmd_names
1439d60 drm/i915: Shrink cxsr_latency_table

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[Intel-gfx] [PATCH 2/6] drm/i915/skl: Remove linetime from skl_wm_values

[Lyude]

Next part of cleaning up the watermark code for skl. This is easy, since
it seems that we never actually needed to keep track of the linetime in
the skl_wm_values struct anyway.

Signed-off-by: Lyude 
Cc: Maarten Lankhorst 
Cc: Ville Syrjälä 
Cc: Matt Roper 
---
 drivers/gpu/drm/i915/i915_drv.h  | 1 -
 drivers/gpu/drm/i915/intel_display.c | 6 --
 drivers/gpu/drm/i915/intel_pm.c  | 7 +--
 3 files changed, 5 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 85e541c..d26e5999 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1643,7 +1643,6 @@ struct skl_ddb_allocation {
 struct skl_wm_values {
unsigned dirty_pipes;
struct skl_ddb_allocation ddb;
-   uint32_t wm_linetime[I915_MAX_PIPES];
uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
 };
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 17733af..a71d05a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14832,6 +14832,8 @@ static void intel_begin_crtc_commit(struct drm_crtc 
*crtc,
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+   struct intel_crtc_state *intel_cstate =
+   to_intel_crtc_state(crtc->state);
struct intel_crtc_state *old_intel_state =
to_intel_crtc_state(old_crtc_state);
bool modeset = needs_modeset(crtc->state);
@@ -14848,13 +14850,13 @@ static void intel_begin_crtc_commit(struct drm_crtc 
*crtc,
intel_color_load_luts(crtc->state);
}
 
-   if (to_intel_crtc_state(crtc->state)->update_pipe)
+   if (intel_cstate->update_pipe)
intel_update_pipe_config(intel_crtc, old_intel_state);
else if (INTEL_GEN(dev_priv) >= 9) {
skl_detach_scalers(intel_crtc);
 
I915_WRITE(PIPE_WM_LINETIME(pipe),
-  dev_priv->wm.skl_hw.wm_linetime[pipe]);
+  intel_cstate->wm.skl.optimal.linetime);
}
 }
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0383516..af96888 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3839,8 +3839,6 @@ static void skl_compute_wm_results(struct drm_device *dev,
temp |= PLANE_WM_EN;
 
r->plane_trans[pipe][PLANE_CURSOR] = temp;
-
-   r->wm_linetime[pipe] = p_wm->linetime;
 }
 
 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
@@ -4069,7 +4067,6 @@ skl_copy_wm_for_pipe(struct skl_wm_values *dst,
 struct skl_wm_values *src,
 enum pipe pipe)
 {
-   dst->wm_linetime[pipe] = src->wm_linetime[pipe];
memcpy(dst->plane[pipe], src->plane[pipe],
   sizeof(dst->plane[pipe]));
memcpy(dst->plane_trans[pipe], src->plane_trans[pipe],
@@ -4320,8 +4317,6 @@ static void skl_pipe_wm_get_hw_state(struct drm_crtc 
*crtc)
 
max_level = ilk_wm_max_level(dev);
 
-   hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
-
for (level = 0; level <= max_level; level++) {
for (i = 0; i < intel_num_planes(intel_crtc); i++)
hw->plane[pipe][i][level] =
@@ -4338,7 +4333,7 @@ static void skl_pipe_wm_get_hw_state(struct drm_crtc 
*crtc)
 
hw->dirty_pipes |= drm_crtc_mask(crtc);
 
-   active->linetime = hw->wm_linetime[pipe];
+   active->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
 
for (level = 0; level <= max_level; level++) {
for (i = 0; i < intel_num_planes(intel_crtc); i++) {
-- 
2.7.4

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[Intel-gfx] [PATCH 1/6] drm/i915/skl: Move per-pipe ddb allocations into crtc states

[Lyude]

First part of cleaning up all of the skl watermark code. This moves the
structures for storing the ddb allocations of each pipe into
intel_crtc_state, along with moving the structures for storing the
current ddb allocations active on hardware into intel_crtc.

Signed-off-by: Lyude 
Cc: Maarten Lankhorst 
Cc: Ville Syrjälä 
Cc: Matt Roper 
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 -
 drivers/gpu/drm/i915/intel_display.c | 16 ---
 drivers/gpu/drm/i915/intel_drv.h |  8 +---
 drivers/gpu/drm/i915/intel_pm.c  | 40 +++-
 4 files changed, 30 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f8c66ee..85e541c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1636,7 +1636,6 @@ static inline bool skl_ddb_entry_equal(const struct 
skl_ddb_entry *e1,
 }
 
 struct skl_ddb_allocation {
-   struct skl_ddb_entry pipe[I915_MAX_PIPES];
struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* 
packed/uv */
struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
 };
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index a366656..17733af 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14235,12 +14235,11 @@ static void skl_update_crtcs(struct drm_atomic_state 
*state,
 unsigned int *crtc_vblank_mask)
 {
struct drm_device *dev = state->dev;
-   struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
struct drm_crtc *crtc;
+   struct intel_crtc *intel_crtc;
struct drm_crtc_state *old_crtc_state;
-   struct skl_ddb_allocation *new_ddb = _state->wm_results.ddb;
-   struct skl_ddb_allocation *cur_ddb = _priv->wm.skl_hw.ddb;
+   struct intel_crtc_state *cstate;
unsigned int updated = 0;
bool progress;
enum pipe pipe;
@@ -14258,12 +14257,14 @@ static void skl_update_crtcs(struct drm_atomic_state 
*state,
for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
bool vbl_wait = false;
unsigned int cmask = drm_crtc_mask(crtc);
-   pipe = to_intel_crtc(crtc)->pipe;
+
+   intel_crtc = to_intel_crtc(crtc);
+   cstate = to_intel_crtc_state(crtc->state);
+   pipe = intel_crtc->pipe;
 
if (updated & cmask || !crtc->state->active)
continue;
-   if (skl_ddb_allocation_overlaps(state, cur_ddb, new_ddb,
-   pipe))
+   if (skl_ddb_allocation_overlaps(state, intel_crtc))
continue;
 
updated |= cmask;
@@ -14274,7 +14275,8 @@ static void skl_update_crtcs(struct drm_atomic_state 
*state,
 * then we need to wait for a vblank to pass for the
 * new ddb allocation to take effect.
 */
-   if (!skl_ddb_allocation_equals(cur_ddb, new_ddb, pipe) 
&&
+   if (!skl_ddb_entry_equal(>wm.skl.ddb,
+_crtc->hw_ddb) &&
!crtc->state->active_changed &&
intel_state->wm_results.dirty_pipes != updated)
vbl_wait = true;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f48e79a..35ba282 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -496,6 +496,7 @@ struct intel_crtc_wm_state {
struct {
/* gen9+ only needs 1-step wm programming */
struct skl_pipe_wm optimal;
+   struct skl_ddb_entry ddb;
 
/* cached plane data rate */
unsigned plane_data_rate[I915_MAX_PLANES];
@@ -733,6 +734,9 @@ struct intel_crtc {
bool cxsr_allowed;
} wm;
 
+   /* gen9+: ddb allocation currently being used */
+   struct skl_ddb_entry hw_ddb;
+
int scanline_offset;
 
struct {
@@ -1755,9 +1759,7 @@ bool skl_ddb_allocation_equals(const struct 
skl_ddb_allocation *old,
   const struct skl_ddb_allocation *new,
   enum pipe pipe);
 bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
-const struct skl_ddb_allocation *old,
-const struct skl_ddb_allocation *new,
-

[Intel-gfx] [PATCH 0/6] Start of skl watermark cleanup

[Lyude]

While it (mostly) works, the code for handling watermarks on Skylake has been
kind of ugly for a while. As well a lot of it isn't that friendly to atomic
transactions, Lots of copy paste, redundant wm values, etc. While this isn't a
full cleanup, it's a good start. As well, we add a couple of features for
making debugging watermarks a little easier.

Cc: Maarten Lankhorst 
Cc: Ville Syrjälä 
Cc: Matt Roper 

Lyude (6):
  drm/i915/skl: Move per-pipe ddb allocations into crtc states
  drm/i915/skl: Remove linetime from skl_wm_values
  drm/i915: Add enable_sagv option
  drm/i915/gen9: Make skl_wm_level per-plane
  drm/i915/gen9: Get rid of redundant watermark values
  drm/i915/gen9: Add ddb changes to atomic debug output

 drivers/gpu/drm/i915/i915_drv.h  |  10 +-
 drivers/gpu/drm/i915/i915_params.c   |   5 +
 drivers/gpu/drm/i915/i915_params.h   |   1 +
 drivers/gpu/drm/i915/intel_display.c |  52 +++--
 drivers/gpu/drm/i915/intel_drv.h |  20 +-
 drivers/gpu/drm/i915/intel_pm.c  | 437 ---
 drivers/gpu/drm/i915/intel_sprite.c  |   8 +-
 7 files changed, 260 insertions(+), 273 deletions(-)

-- 
2.7.4

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[Intel-gfx] [PATCH 3/6] drm/i915: Add enable_sagv option

[Lyude]

This option allows us to manually control the SAGV at module load time.
This can be useful in situations such as trying to debug watermark
changes, since enabled SAGV + incorrect watermarks = total GPU
annihilation.

Signed-off-by: Lyude 
Cc: Maarten Lankhorst 
Cc: Ville Syrjälä 
Cc: Matt Roper 
---
 drivers/gpu/drm/i915/i915_params.c   |  5 +
 drivers/gpu/drm/i915/i915_params.h   |  1 +
 drivers/gpu/drm/i915/intel_display.c | 16 +---
 3 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 768ad89..f462cd4 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -62,6 +62,7 @@ struct i915_params i915 __read_mostly = {
.inject_load_failure = 0,
.enable_dpcd_backlight = false,
.enable_gvt = false,
+   .enable_sagv = -1,
 };
 
 module_param_named(modeset, i915.modeset, int, 0400);
@@ -233,3 +234,7 @@ MODULE_PARM_DESC(enable_dpcd_backlight,
 module_param_named(enable_gvt, i915.enable_gvt, bool, 0400);
 MODULE_PARM_DESC(enable_gvt,
"Enable support for Intel GVT-g graphics virtualization host 
support(default:false)");
+
+module_param_named_unsafe(enable_sagv, i915.enable_sagv, int, 0400);
+MODULE_PARM_DESC(enable_sagv,
+   "Enable the SAGV (gen9+ only)(1=enabled, 0=disabled, -1=driver 
discretion [default])");
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 3a0dd78..a7db125 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -65,6 +65,7 @@ struct i915_params {
bool enable_dp_mst;
bool enable_dpcd_backlight;
bool enable_gvt;
+   int enable_sagv;
 };
 
 extern struct i915_params i915 __read_mostly;
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index a71d05a..dd15ae2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -16904,12 +16904,22 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
pll->on = false;
}
 
-   if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+   if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
vlv_wm_get_hw_state(dev);
-   else if (IS_GEN9(dev))
+   } else if (IS_GEN9(dev)) {
skl_wm_get_hw_state(dev);
-   else if (HAS_PCH_SPLIT(dev))
+
+   if (i915.enable_sagv != -1) {
+   if (i915.enable_sagv)
+   intel_enable_sagv(dev_priv);
+   else
+   intel_disable_sagv(dev_priv);
+
+   dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
+   }
+   } else if (HAS_PCH_SPLIT(dev)) {
ilk_wm_get_hw_state(dev);
+   }
 
for_each_intel_crtc(dev, crtc) {
unsigned long put_domains;
-- 
2.7.4

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[Intel-gfx] [PATCH 6/6] drm/i915/gen9: Add ddb changes to atomic debug output

[Lyude]

Finally, add some debugging output for ddb changes in the atomic debug
output. This makes it a lot easier to spot bugs from incorrect ddb
allocations.

Signed-off-by: Lyude 
Cc: Maarten Lankhorst 
Cc: Ville Syrjälä 
Cc: Matt Roper 
---
 drivers/gpu/drm/i915/intel_pm.c | 57 +
 1 file changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7708646..2691428 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4030,6 +4030,61 @@ skl_copy_wm_for_pipe(struct skl_wm_values *dst,
   sizeof(dst->ddb.plane[pipe]));
 }
 
+static void
+skl_print_wm_changes(const struct drm_atomic_state *state)
+{
+   const struct drm_device *dev = state->dev;
+   const struct drm_i915_private *dev_priv = to_i915(dev);
+   const struct intel_atomic_state *intel_state =
+   to_intel_atomic_state(state);
+   const struct drm_crtc *crtc;
+   const struct drm_crtc_state *cstate;
+   const struct drm_plane *plane;
+   const struct intel_plane *intel_plane;
+   const struct drm_plane_state *pstate;
+   const struct skl_ddb_allocation *old_ddb = _priv->wm.skl_hw.ddb;
+   const struct skl_ddb_allocation *new_ddb = _state->wm_results.ddb;
+   enum pipe pipe;
+   int id;
+   int i, j;
+
+   for_each_crtc_in_state(state, crtc, cstate, i) {
+   if (!crtc->state)
+   continue;
+
+   pipe = to_intel_crtc(crtc)->pipe;
+
+   for_each_plane_in_state(state, plane, pstate, j) {
+   const struct skl_ddb_entry *old, *new;
+
+   intel_plane = to_intel_plane(plane);
+   id = skl_wm_plane_id(intel_plane);
+   old = _ddb->plane[pipe][id];
+   new = _ddb->plane[pipe][id];
+
+   if (intel_plane->pipe != pipe)
+   continue;
+
+   if (skl_ddb_entry_equal(old, new))
+   continue;
+
+   if (id != PLANE_CURSOR) {
+   DRM_DEBUG_ATOMIC("[PLANE:%d:plane %d%c] ddb (%d 
- %d) -> (%d - %d)\n",
+plane->base.id, id + 1,
+pipe_name(pipe),
+old->start, old->end,
+new->start, new->end);
+   } else {
+   DRM_DEBUG_ATOMIC("[PLANE:%d:cursor %c] ddb (%d 
- %d) -> (%d - %d)\n",
+plane->base.id,
+pipe_name(pipe),
+old->start, old->end,
+new->start, new->end);
+   }
+   }
+   }
+}
+
 static int
 skl_compute_wm(struct drm_atomic_state *state)
 {
@@ -4091,6 +4146,8 @@ skl_compute_wm(struct drm_atomic_state *state)
intel_cstate->update_wm_pre = true;
}
 
+   skl_print_wm_changes(state);
+
return 0;
 }
 
-- 
2.7.4

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[Intel-gfx] [PATCH 5/6] drm/i915/gen9: Get rid of redundant watermark values

[Lyude]

Now that we've make skl_wm_levels make a little more sense, we can
remove all of the redundant wm information. Up until now we'd been
storing two copies of all of the skl watermarks: one being the
skl_pipe_wm structs, the other being the global wm struct in
drm_i915_private containing the raw register values. This is confusing
and problematic, since it means we're prone to accidentally letting the
two copies go out of sync. So, get rid of all of the functions
responsible for computing the register values and just use a single
helper, skl_write_wm_level(), to convert and write the new watermarks on
the fly.

Signed-off-by: Lyude 
Cc: Maarten Lankhorst 
Cc: Ville Syrjälä 
Cc: Matt Roper 
---
 drivers/gpu/drm/i915/i915_drv.h  |   2 -
 drivers/gpu/drm/i915/intel_display.c |  14 ++-
 drivers/gpu/drm/i915/intel_drv.h |   6 +-
 drivers/gpu/drm/i915/intel_pm.c  | 203 ---
 drivers/gpu/drm/i915/intel_sprite.c  |   8 +-
 5 files changed, 88 insertions(+), 145 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0f97d43..63519ac 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1643,8 +1643,6 @@ struct skl_ddb_allocation {
 struct skl_wm_values {
unsigned dirty_pipes;
struct skl_ddb_allocation ddb;
-   uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
-   uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
 };
 
 struct skl_wm_level {
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index dd15ae2..c580d3d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3378,6 +3378,8 @@ static void skylake_update_primary_plane(struct drm_plane 
*plane,
struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_framebuffer *fb = plane_state->base.fb;
const struct skl_wm_values *wm = _priv->wm.skl_results;
+   const struct skl_plane_wm *p_wm =
+   _state->wm.skl.optimal.planes[0];
int pipe = intel_crtc->pipe;
u32 plane_ctl;
unsigned int rotation = plane_state->base.rotation;
@@ -3414,7 +3416,7 @@ static void skylake_update_primary_plane(struct drm_plane 
*plane,
intel_crtc->adjusted_y = src_y;
 
if (wm->dirty_pipes & drm_crtc_mask(_crtc->base))
-   skl_write_plane_wm(intel_crtc, wm, 0);
+   skl_write_plane_wm(intel_crtc, p_wm, >ddb, 0);
 
I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
@@ -3448,6 +3450,8 @@ static void skylake_disable_primary_plane(struct 
drm_plane *primary,
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+   struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
+   const struct skl_plane_wm *p_wm = >wm.skl.optimal.planes[0];
int pipe = intel_crtc->pipe;
 
/*
@@ -3455,7 +3459,8 @@ static void skylake_disable_primary_plane(struct 
drm_plane *primary,
 * plane's visiblity isn't actually changing neither is its watermarks.
 */
if (!crtc->primary->state->visible)
-   skl_write_plane_wm(intel_crtc, _priv->wm.skl_results, 0);
+   skl_write_plane_wm(intel_crtc, p_wm,
+  _priv->wm.skl_results.ddb, 0);
 
I915_WRITE(PLANE_CTL(pipe, 0), 0);
I915_WRITE(PLANE_SURF(pipe, 0), 0);
@@ -10819,12 +10824,15 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, 
u32 base,
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+   struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
const struct skl_wm_values *wm = _priv->wm.skl_results;
+   const struct skl_plane_wm *p_wm =
+   >wm.skl.optimal.planes[PLANE_CURSOR];
int pipe = intel_crtc->pipe;
uint32_t cntl = 0;
 
if (INTEL_GEN(dev_priv) >= 9 && wm->dirty_pipes & drm_crtc_mask(crtc))
-   skl_write_cursor_wm(intel_crtc, wm);
+   skl_write_cursor_wm(intel_crtc, p_wm, >ddb);
 
if (plane_state && plane_state->base.visible) {
cntl = MCURSOR_GAMMA_ENABLE;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d684f4f..958dc72 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1765,9 +1765,11 @@ bool skl_ddb_allocation_equals(const struct 
skl_ddb_allocation *old,
 bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
 struct intel_crtc *intel_crtc);
 void 

Re: [Intel-gfx] [Regression report] Weekly regression report WW40

[Argotti, Yann]

> > On Mon, 03 Oct 2016, Jairo Miramontes
> >  wrote:
> > > This week regressions
> >
> > In the past we used "regression", "bisect_pending", and "bisected" in
> > the bugzilla "Keywords" field. Can we start using those again, please?
> 
> I think this is a very good idea Jani. So we can start to scrub current
> regression (and then igt linked one) and update accordingly.
> Yann

Two additional thoughts are:
- add "regression_pending" (vs "regression") as well as keyword to indicate 
where bug reporter has doubt on the fact it is or not a regression.
- either use of "regression" or "regression_pending" must be coming with good & 
bad commit when reporting the bug
Yann

> 
> >
> > BR,
> > Jani.
> >
> >
> > --
> > Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] [PATCH 04/22] drm/i915: Make HAS_DDI and HAS_PCH_LPT_LP only take dev_priv

[Ville Syrjälä]

On Wed, Oct 05, 2016 at 01:33:31PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> This saves 3248 bytes of .rodata strings.
> 
> Signed-off-by: Tvrtko Ursulin 
> ---
>  drivers/gpu/drm/i915/i915_drv.h   |  8 +++---
>  drivers/gpu/drm/i915/intel_crt.c  | 10 +++
>  drivers/gpu/drm/i915/intel_display.c  | 49 
> ++-
>  drivers/gpu/drm/i915/intel_dp.c   | 16 ++--
>  drivers/gpu/drm/i915/intel_dpll_mgr.c |  4 +--
>  drivers/gpu/drm/i915/intel_hdmi.c | 10 +++
>  drivers/gpu/drm/i915/intel_pm.c   |  4 +--
>  drivers/gpu/drm/i915/intel_psr.c  |  8 +++---
>  8 files changed, 56 insertions(+), 53 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4613f031d127..61e0cf7374ed 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2817,7 +2817,7 @@ struct drm_i915_cmd_table {
>  
>  #define HAS_DP_MST(dev)  (INTEL_INFO(dev)->has_dp_mst)
>  
> -#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
> +#define HAS_DDI(dev_priv)(dev_priv->info.has_ddi)

((dev_priv)->...)

>  #define HAS_FPGA_DBG_UNCLAIMED(dev)  (INTEL_INFO(dev)->has_fpga_dbg)
>  #define HAS_PSR(dev) (INTEL_INFO(dev)->has_psr)
>  #define HAS_RUNTIME_PM(dev)  (INTEL_INFO(dev)->has_runtime_pm)
> @@ -2856,8 +2856,10 @@ struct drm_i915_cmd_table {
>  #define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
>  #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
>  #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
> -#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == 
> INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
> -#define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == 
> INTEL_PCH_LPT_DEVICE_ID_TYPE)
> +#define HAS_PCH_LPT_LP(dev_priv) \
> + (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
> +#define HAS_PCH_LPT_H(dev_priv) \
> + (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
>  #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
>  #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
>  #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
> diff --git a/drivers/gpu/drm/i915/intel_crt.c 
> b/drivers/gpu/drm/i915/intel_crt.c
> index 88ebbdde185a..227eaf270226 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -280,13 +280,13 @@ static bool intel_crt_compute_config(struct 
> intel_encoder *encoder,
>struct intel_crtc_state *pipe_config,
>struct drm_connector_state *conn_state)
>  {
> - struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  
> - if (HAS_PCH_SPLIT(dev))
> + if (HAS_PCH_SPLIT(dev_priv))
>   pipe_config->has_pch_encoder = true;
>  
>   /* LPT FDI RX only supports 8bpc. */
> - if (HAS_PCH_LPT(dev)) {
> + if (HAS_PCH_LPT(dev_priv)) {
>   if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
>   DRM_DEBUG_KMS("LPT only supports 24bpp\n");
>   return false;
> @@ -296,7 +296,7 @@ static bool intel_crt_compute_config(struct intel_encoder 
> *encoder,
>   }
>  
>   /* FDI must always be 2.7 GHz */
> - if (HAS_DDI(dev))
> + if (HAS_DDI(dev_priv))
>   pipe_config->port_clock = 135000 * 2;
>  
>   return true;
> @@ -916,7 +916,7 @@ void intel_crt_init(struct drm_device *dev)
>   crt->base.enable = intel_enable_crt;
>   if (I915_HAS_HOTPLUG(dev))
>   crt->base.hpd_pin = HPD_CRT;
> - if (HAS_DDI(dev)) {
> + if (HAS_DDI(dev_priv)) {
>   crt->base.port = PORT_E;
>   crt->base.get_config = hsw_crt_get_config;
>   crt->base.get_hw_state = intel_ddi_get_hw_state;
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index a366656bcec5..235df123ac50 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1187,19 +1187,17 @@ void assert_fdi_rx_pll(struct drm_i915_private 
> *dev_priv,
>   onoff(state), onoff(cur_state));
>  }
>  
> -void assert_panel_unlocked(struct drm_i915_private *dev_priv,
> -enum pipe pipe)
> +void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
>  {
> - struct drm_device *dev = _priv->drm;
>   i915_reg_t pp_reg;
>   u32 val;
>   enum pipe panel_pipe = PIPE_A;
>   bool locked = true;
>  
> - if (WARN_ON(HAS_DDI(dev)))
> + if (WARN_ON(HAS_DDI(dev_priv)))
>   return;
>  
> - if (HAS_PCH_SPLIT(dev)) {
> + if (HAS_PCH_SPLIT(dev_priv)) {
>   u32 port_sel;
>  
>   pp_reg = PP_CONTROL(0);
> @@ -1209,7 +1207,7 @@ void assert_panel_unlocked(struct drm_i915_private 
> *dev_priv,
>